LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 310

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
19.14.7 Compare <address1> <address2> <no of bytes>
19.14.8 Reinvoke ISP
19.14.9 ReadUID
Table 315. IAP Compare command
Table 316. Reinvoke ISP
Table 317. IAP ReadUID command
Command
Input
Return Code
Result
Description
Command
Input
Return Code
Result
Description
Command
Input
Return Code
Result
Description
Compare
Command code: 5610
Param0(DST): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param1(SRC): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.
CMD_SUCCESS |
COMPARE_ERROR |
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED
Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.
This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes any
of the first 512 bytes starting from address zero. The first 512 bytes can be
re-mapped to RAM.
Compare
Command code: 5710
None
None.
This command is used to invoke the bootloader in ISP mode. It maps boot
vectors, sets PCLK = CCLK, configures UART pins RXD and TXD, resets
counter/timer CT32B1 and resets the U0FDR (see
may be used when a valid user program is present in the internal flash memory
and the PIO0_1 pin is not accessible to force the ISP mode.
Compare
Command code: 5810
CMD_SUCCESS
Result0: The first 32-bit word (at the lowest address).
Result1: The second 32-bit word.
Result2: The third 32-bit word.
Result3: The fourth 32-bit word.
This command is used to read the unique ID.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
Table
202). This command
UM10375
© NXP B.V. 2010. All rights reserved.
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