LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 38

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
3.5.45 Wake-up configuration register
Table 50.
The bits in this register can be programmed to determine the state the chip must enter
when it is waking up from Deep-sleep mode.
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 51.
Bit
6
11:7
31:12
Bit
0
1
2
3
4
5
6
Symbol
WDTOSC_PD
-
-
Symbol
IRCOUT_PD
IRC_PD
FLASH_PD
BOD_PD
ADC_PD
SYSOSC_PD
WDTOSC_PD
description
Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
All information provided in this document is subject to legal disclaimers.
…continued
Rev. 2 — 7 July 2010
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Value
0
1
11111
0
Description
IRC oscillator output wake-up configuration
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IRC oscillator power-down wake-up configuration
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Flash wake-up configuration
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BOD wake-up configuration
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ADC wake-up configuration
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System oscillator wake-up configuration
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Watchdog oscillator wake-up configuration
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Description
Watchdog oscillator power control in Deep-sleep
mode, see
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Reserved. Always write these bits as 11111.
Reserved
Table
Chapter 3: LPC13xx System configuration
49.
UM10375
© NXP B.V. 2010. All rights reserved.
39 of 333
Reset
value
0
0
0
Reset
value
0
0
0
0
1
1
1