LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 50
LPC1342FHN33,551
Manufacturer Part Number
LPC1342FHN33,551
Description
IC MCU 32BIT 16KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1342FHN33,551
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
4 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4946
935289656551
935289656551
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4.1 Introduction
4.2 Register description
UM10375
User manual
4.2.1 Power control register
The PMU controls the Deep power-down mode. Four general purpose register in the PMU
can be used to retain data during Deep power-down mode.
Table 57.
The power control register selects whether one of the ARM Cortex-M3 controlled
power-down modes (Sleep mode or Deep-sleep mode) or the Deep power-down mode is
entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down
modes respectively. See
Table 58.
Name
PCON
GPREG0
GPREG1
GPREG2
GPREG3
GPREG4
Bit
0
1
7:2
8
10:9
UM10375
Chapter 4: LPC13xx Power Management Unit (PMU)
Rev. 2 — 7 July 2010
Symbol
-
DPDEN
-
SLEEPFLAG
-
Register overview: PMU (base address 0x4003 8000)
Power control register (PCON, address 0x4003 8000) bit description
All information provided in this document is subject to legal disclaimers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
Value
-
0
1
-
0
1
-
Rev. 2 — 7 July 2010
Section 3.8
Description
Reserved. Do not write 1 to this bit.
Deep power-down mode enable
ARM WFI will enter Sleep or Deep-sleep mode (clock to
ARM Cortex-M3 core turned off).
ARM WFI will enter Deep-power down mode (ARM
Cortex-M3 core powered-down).
Reserved. Do not write ones to this bit.
Sleep mode flag
Read: No power-down mode entered. LPC13xx is in Run
mode.
Write: No effect.
Read: Sleep/Deep-sleep or Deep power-down mode
entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
Reserved. Do not write ones to this bit.
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
for details on how to enter the power-down modes.
Description
Power control register
General purpose register 0
General purpose register 1
General purpose register 2
General purpose register 3
General purpose register 4
© NXP B.V. 2010. All rights reserved.
User manual
Reset
value
0x0
0x0
0x0
0x0
0x0
0x0
51 of 333
Reset
value
0x0
0
0x0
0
0x0
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