LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 59

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
5.6.4 Interrupt Clear-Enable Register 1 register
Table 65.
The ICER1 register allows disabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Enabling interrupts is done through the
ISER0 and ISER1 registers
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 66.
Bit
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
0
1
2
3
4
5
6
7
8
Name
ICE_PIO1_0
ICE_PIO1_1
ICE_PIO1_2
ICE_PIO1_3
ICE_PIO1_4
ICE_PIO1_5
ICE_PIO1_6
ICE_PIO1_7
ICE_PIO1_8
ICE_PIO1_9
ICE_PIO1_10
ICE_PIO1_11
ICE_PIO2_0
ICE_PIO2_1
ICE_PIO2_2
ICE_PIO2_3
ICE_PIO2_4
ICE_PIO2_5
ICE_PIO2_6
ICE_PIO2_7
Name
ICE_PIO2_8
ICE_PIO2_9
ICE_PIO2_10
ICE_PIO2_11
ICE_PIO3_0
ICE_PIO3_1
ICE_PIO3_2
ICE_PIO3_3
ICE_I2C0
Interrupt Clear-Enable Register 0
Interrupt Clear-Enable Register 1 register (ICER1 - address 0xE000 E184) bit
description
All information provided in this document is subject to legal disclaimers.
Description
PIO1_0 start logic input interrupt disable.
PIO1_1 start logic input interrupt disable.
PIO1_2 start logic input interrupt disable.
PIO1_3 start logic input interrupt disable.
PIO1_4 start logic input interrupt disable.
PIO1_5 start logic input interrupt disable.
PIO1_6 start logic input interrupt disable.
PIO1_7 start logic input interrupt disable.
PIO1_8 start logic input interrupt disable.
PIO1_9 start logic input interrupt disable.
PIO1_10 start logic input interrupt disable.
PIO1_11 start logic input interrupt disable.
PIO2_0 start logic input interrupt disable.
PIO2_1 start logic input interrupt disable.
PIO2_2 start logic input interrupt disable.
PIO2_3 start logic input interrupt disable.
PIO2_4 start logic input interrupt disable.
PIO2_5 start logic input interrupt disable.
PIO2_6 start logic input interrupt disable.
PIO2_7 start logic input interrupt disable.
Description
PIO0_0 start logic input interrupt disable.
PIO2_9 start logic input interrupt disable.
PIO2_10 start logic input interrupt disable.
PIO2_11 start logic input interrupt disable.
PIO3_0 start logic input interrupt disable.
PIO3_0 start logic input interrupt disable.
PIO3_0 start logic input interrupt disable.
PIO3_0 start logic input interrupt disable.
I
2
Rev. 2 — 7 July 2010
C0 interrupt disable.
(Section 5.6.1
and
…continued
Chapter 5: LPC13xx Interrupt controller
Section
5.6.2).
UM10375
© NXP B.V. 2010. All rights reserved.
60 of 333