P89V52X2FA,512 NXP Semiconductors, P89V52X2FA,512 Datasheet - Page 33

• Manufacturer Part Number: P89V52X2FA,512
• Description: IC 80C51 MCU FLASH 8K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V52X2FA,512

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 44-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Eeprom Size: 192 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM11011 - BOARD FOR P89V52X2 44-TQFP622-1017 - BOARD 44-ZIF PLCC SOCKET622-1012 - BOARD FOR P89V52X2 44-TQFP622-1008 - BOARD FOR LPC9103 10-HVSON622-1002 - USB IN-CIRCUIT PROG LPC9XX
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4249-5; 935282528512; P89V52X2FA

NXP Semiconductors
Table 31.
P89V52X2_3
Product data sheet
Mode
Idle mode
Power-down
mode
Power-saving modes
6.12.2 Power-down mode
6.13 Data EEPROM
Initiated by
Software (set IDL bit in
PCON)
MOV PCON, #01H;
Software (set PD bit in
PCON)
MOV PCON, #02H;
The device exits Idle mode through either a system interrupt or a hardware reset. Exiting
Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle
mode. After exit the Interrupt Service Routine, the interrupted program resumes execution
beginning at the instruction immediately following the instruction which invoked the Idle
mode. A hardware reset starts the device similar to a power-on reset.
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down, the minimum
V
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin LOW restarts the oscillator, the signal must
hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit.
Upon interrupt signal restored to logic V
resumes beginning at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be executed
before the V
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
The P89V52X2 contains 192 B of data EEPROM organized into three pages of 64 B
each. This memory can be erased in 64 byte pages (using a Page Erase command) or
erased and written as bytes. The P89V52X2 flash reliably stores memory contents even
after 100000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. P89V52X2 uses V
Program/Erase algorithms.
DD
level is 2.0 V.
DD
line is restored to its normal operating voltage. Be sure to hold V
State of device
CLK is running. Interrupts,
serial port and timers/counters
are active. Program Counter is
stopped. ALE and PSEN
signals at a HIGH-level during
Idle. All registers remain
unchanged.
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-level during power-down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Rev. 03 — 4 May 2009
IH
, the interrupt service routine program execution
80C51 with 256 B RAM, 192 B data EEPROM
DD
Exited by
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode,
after the interrupt service routine RETI
instruction, program resumes execution
beginning at the instruction following the one
that invoked Idle mode. A hardware reset
restarts the device similar to a power-on
reset.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
interrupt service routine RETI instruction
program resumes execution beginning at
the instruction following the one that invoked
Power-down mode. A hardware reset
restarts the device similar to a power-on
reset.
as the supply voltage to perform the
P89V52X2
© NXP B.V. 2009. All rights reserved.
DD
voltage
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