P89V52X2FA,512 NXP Semiconductors, P89V52X2FA,512 Datasheet
P89V52X2FA,512
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935282528512
P89V52X2FA
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P89V52X2FA,512 Summary of contents
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P89V52X2 8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM Rev. 03 — 4 May 2009 1. General description The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89V52X2FN P89V52X2FBD P89V52X2FA 4. Block diagram P89V52X2 P3[7:0] P2[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89V52X2_3 Product data sheet Ordering information Package Name Description DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 LQFP44 plastic low profi ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. DIP40 pin configuration P89V52X2_3 Product data sheet 80C51 with 256 B RAM, 192 B data EEPROM 1 40 P1[0]/T2 P1[1]/T2EX 2 39 P1[ P1[ P1[4] P1[ P1[ P1[7] RST 9 32 P3[0]/RXD 10 31 P89V52X2 P3[1]/TXD P3[2]/INT0 ...
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... NXP Semiconductors Fig 3. PLCC44 pin configuration Fig 4. LQFP44 pin configuration P89V52X2_3 Product data sheet 80C51 with 256 B RAM, 192 B data EEPROM P1[5] 7 P1[ P1[7] RST 10 P3[0]/RXD 11 P89V52X2 12 n.c. 13 P3[1]/TXD P3[2]/INT0 14 P3[3]/INT1 15 16 P3[4]/T0 P3[5]/T1 17 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin DIP40 LQFP44 P0[0] to P0[7] P0[0]/AD0 39 37 P0[1]/AD1 38 36 P0[2]/AD2 37 35 P0[3]/AD3 36 34 P0[4]/AD4 35 33 P0[5]/AD5 34 32 P0[6]/AD6 33 31 P0[7]/AD7 32 30 P1[0] to P1[7] P1[0]/T2 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin DIP40 LQFP44 P1[ P2[0] to P2[7] P2[0]/ P2[1]/ P2[2]/A10 23 20 P2[3]/A11 24 21 P2[4]/A12 25 22 P2[5]/A13 26 23 P2[6]/A14 27 24 P2[7]/A15 28 25 P3[0] to P3[7] P3[0]/RXD 10 5 P3[1]/TXD 11 7 P3[2]/INT0 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin DIP40 LQFP44 P3[5]/ P3[6]/ P3[7]/ PSEN 29 26 RST ALE 30 27 XTAL1 19 15 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor ...
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... NXP Semiconductors 6. Functional description 6.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 3. Special function registers * indicates SFRs that are bit addressable. Name Description Bit address ACC* Accumulator AUXR Auxiliary function register AUXR1 Auxiliary function register 1 Bit address B* B register CKCON B register DPTR Data Pointer (2 ...
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Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit address PSW* Program Status Word RCAP2H Timer2 Capture HIGH RCAP2L Timer2 Capture LOW Bit address SCON* Serial Port Control SBUF Serial Port Data ...
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... NXP Semiconductors 6.2 Memory organization The various P89V52X2 memory spaces are as follows: • DATA 128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. ...
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... NXP Semiconductors Fig 5. Oscillator characteristics (using the on-chip oscillator) Fig 6. Oscillator characteristics (external clock drive) 6.3.2 Clock control register (CKCON) By default, the device runs at twelve clocks per machine cycle. The device may be run in 6 clock per machine cycle mode by programming of either a non-volatile bit (FX2 SFR bit (Table 5 “ ...
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... NXP Semiconductors Table 7. Bit Fig 7. Internal and external data memory structure 6.5 Dual data pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1 (see Fig 8 ...
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... NXP Semiconductors Table 9. Bit 6.6 Reset At initial power-up, the port pins will random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the device to start executing instructions from an indeterminate location. Such undefi ...
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... NXP Semiconductors 6.7 Flash memory 6.7.1 Flash organization The P89V52X2 program memory consists block of user code. The flash can be read or written in bytes but may only be erased as an entire block. A chip erase function will erase the entire user code memory and its associated security bits. This flash memory can be erased or programmed using a programmer tool that supports ICP ...
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... NXP Semiconductors Table 11. Bit Table 12 Table 13. Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset Bit Symbol Table 14. Bit P89V52X2_3 Product data sheet TMOD - Timer/Counter mode control register (address 89H) bit description Symbol Description T1GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is HIGH and the TR1 control pin is set ...
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... NXP Semiconductors Table 14. Bit 6.8.1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a fixed divide-by-32 prescaler. osc/6 Tn pin TnGate INTn pin Fig 10. Timer/Counter Mode 0 (13-bit counter) In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt fl ...
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... NXP Semiconductors osc/6 Tn pin TRn TnGate INTn pin Fig 11. Timer/Counter Mode 1 (16-bit counter) 6.8.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1. ...
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... NXP Semiconductors TnGate INT0 pin Fig 13. Timer/Counter 0 Mode 3 (two 8-bit counters) 6.9 Timer 2 Timer 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate ...
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... NXP Semiconductors Table 17. Bit Table 18. Not bit addressable; Reset value: XX00 0000B Bit Symbol Table 19. Bit 6.9.1 Capture mode In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overfl ...
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... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 14. Timer 2 in Capture mode This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2 captured into registers RCAP2L and RCAP2H, respectively ...
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... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 15. Timer 2 in auto-reload mode (DCEN = 0) In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overfl ...
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... NXP Semiconductors OSC pin Fig 16. Timer 2 in Auto Reload mode (DCEN = 1) When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external fl ...
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... NXP Semiconductors used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. Figure 17 OSC T2 pin Fig 17 ...
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... NXP Semiconductors When Timer the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors ...
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... NXP Semiconductors 6.10.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 6 ...
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... NXP Semiconductors Table 22. Bit Table 23. SM0, SM1 6.10.5 Framing error Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON. SMOD0 = 0, SCON.7 is the SM0 bit for the UART recommended that SM0 is set up before SMOD0 is set to ‘1’. 6.10.6 More about UART mode 1 Reception is initiated by a detected 1-to-0 transition at RXD ...
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... NXP Semiconductors The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: ( and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the fi ...
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... NXP Semiconductors Fig 18. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when The following examples will help to show the versatility of this scheme. Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1101 --------------------------------------------------- - Given = 1100 00X0 Example 2, slave 1: SADDR = 1100 0000 ...
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... NXP Semiconductors SADDR = 1100 0000 SADEN = 1111 1001 --------------------------------------------------- - Given = 1100 0XX0 Example 2, slave 1: SADDR = 1110 0000 SADEN = 1111 1010 --------------------------------------------------- - Given = 1110 0X0X Example 2, slave 2: SADDR = 1100 0000 SADEN = 1111 1100 --------------------------------------------------- - Given = 1100 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. ...
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... NXP Semiconductors 0 INT0# IT0 IE0 1 TF0 0 INT1# IT1 IE1 1 TF1 RI TI TF2 EXF2 individual enables Fig 19. Interrupt structure Table 25. Bit addressable; Reset value: 00H Bit Symbol Table 26. Bit P89V52X2_3 Product data sheet IP/IPH/IPA/IPAH IE and IEA registers registers global disable IE - Interrupt enable register (address A8H) bit allocation ...
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... NXP Semiconductors Table 26. Bit Table 27. Bit addressable; Reset value: 00H Bit Symbol Table 28. Bit 7 Table 29. Not bit addressable; Reset value: 00H Bit Symbol Table 30. Bit 7 6.12 Power-saving modes The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and Power-down, see 6 ...
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... NXP Semiconductors The device exits Idle mode through either a system interrupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode ...
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... NXP Semiconductors The data EEPROM must be mapped into the code memory address space in order to read, erase, or program the data EEPROM. The memory is read using the MOVC instruction. 6.13.1 Features • ICP with industry-standard commercial programmers • IAP-Lite allows individual and multiple bytes of data EEPROM to be programmed under control of the end application. • ...
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... NXP Semiconductors • Map the data EEPROM into code memory space if not already mapped. • Write the data EEPROM byte address into the DPTR. • Use the MOVC instruction to read the data EEPROM. 6.13.5 Erasing a complete page ( complete page can be erased by performing the following sequence: • ...
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... NXP Semiconductors Writing either the PROG or EP command to FMCON will start the program or erase-program process and place the CPU in a program-idle state. The CPU will remain in this idle state until the program or erase-program cycle is completed. Interrupts will NOT be serviced until the cycle is completed. ...
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... NXP Semiconductors Table 34. Flash Memory Control register (FMCON - address E4H) bit description Bit Symbol Access Description 0 ERR R Set when either of the following conditions occur: • • • FMCMD.0 W Command byte bit Security violation. Set when an attempt is made to program, erase, or CRC a secured page. ...
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... NXP Semiconductors LOAD EP PGM_USER: LOAD_PAGE: BAD: A C-language routine to load the page register and perform an erase/program operation is shown below. This code assumes the data EEPROM has been mapped into user code space. #include <REGV52.H> unsigned char idata dbytes[64];// data buffer unsigned char Fm_stat;// status result bit PGM_USER (unsigned char, unsigned char) ...
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... NXP Semiconductors } 6.13.7 Data EEPROM write enable The data EEPROM has a Write Enable mechanism to help prevent against inadvertent writes. If the WE bit (FMCON.6) is set writes to the data EEPROM are enabled. When cleared, writes are disabled. This bit only affects execution mode. The WE bit is set when: • ...
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... NXP Semiconductors Table 37. Mnemonic CLR_WE CRC_DP EP ERS_DP LOAD MAP PROG SET_WE UNMAP 6.14 User configuration bytes This device contains some non-volatile bytes which allow the user to configure the device. These bytes are programmed or read using the configuration read or write command (CONF) with a programmer that supports ICP. The user confi ...
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... NXP Semiconductors Table 40. Bit 6.16 Code security (CSEC) bits The code security bits protect against software piracy and prevent the contents of the flash from being read by unauthorized parties. The code security bits and their effects are shown in Table 41. Bit Symbol Table 42. ...
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... NXP Semiconductors 7. Limiting values Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. Symbol Parameter T bias ambient temperature amb(bias) ...
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... NXP Semiconductors Table 44. Static characteristics + 2 5 amb DD Symbol Parameter R pull-down pd resistance C input capacitance iss I operating supply DD(oper) current I Idle mode supply DD(idle) current I Power-down mode DD(pd) supply current [1] This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... NXP Semiconductors (mA (1) Maximum I DD(oper) (2) Typical I DD(oper) (3) Maximum I DD(idle) (4) Typical I DD(idle) Fig 20. I vs. frequency DD P89V52X2_3 Product data sheet 80C51 with 256 B RAM, 192 B data EEPROM 10 20 Rev. 03 — 4 May 2009 P89V52X2 002aad196 (1) (2) (3) ( clock frequency (MHz) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9. Dynamic characteristics Table 45. Dynamic characteristics Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = + 2 5 amb DD Symbol Parameter f oscillator frequency osc t ALE pulse width LHLL t address valid to ALE LOW time AVLL ...
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... NXP Semiconductors 9.1 Explanation of symbols Each timing symbol has 5 characters. The first character is always a ‘t’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — ...
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... NXP Semiconductors ALE PSEN RD t LLAX t AVLL port 0 from RI to DPL port 2 Fig 22. External data memory read cycle t LHLL ALE PSEN WR t AVLL from RI or DPL port 0 port 2 Fig 23. External data memory write cycle P89V52X2_3 Product data sheet t LLDV t t LLWL ...
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... NXP Semiconductors Table 46. External clock drive Symbol Parameter f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Fig 24. External clock drive waveform (with an amplitude of at least V Table 47. ...
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... NXP Semiconductors instruction ALE clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 25. Shift register mode timing waveforms Fig 26. Test load example Fig 27. I P89V52X2_3 Product data sheet T XLXL t XHQX XHDX valid valid valid valid to DUT V DD (n.c.) clock ...
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... NXP Semiconductors Fig 28. I Fig 29. I P89V52X2_3 Product data sheet (n.c.) clock signal All other pins disconnected test condition, Idle mode RST XTAL2 (n.c.) XTAL1 V SS All other pins disconnected test condition, Power-down mode DD Rev. 03 — 4 May 2009 P89V52X2 80C51 with 256 B RAM, 192 B data EEPROM ...
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... NXP Semiconductors 10. Package outline DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 4 inches 0.19 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors LQFP44: plastic low profile quad flat package; 44 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT389-1 136E08 Fig 31 ...
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... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 48. Acronym CRC EEPROM EMI IAP I/O LSB MSB PWM RC RETI SFR UART P89V52X2_3 Product data sheet Acronym list Description Cyclic Redundancy Check Electrically Erasable Programmable Read-Only Memory ElectroMagnetic Interference In-Application Programming Input/Output Least Significant Bit Most Significant Bit ...
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... NXP Semiconductors 12. Revision history Table 49. Revision history Document ID Release date P89V52X2_3 20090504 • Modifications: Table • Table P89V52X2_2 20080522 • Modifications: Table 3: added registers FMCON, FMDATA, FMADRH and FMADRL • Table 33: changed address of register FMCON to F4H • Figure 1: corrected XTAL pin names • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 8 6.1 Special function registers . . . . . . . . . . . . . . . . . 8 6.2 Memory organization . . . . . . . . . . . . . . . . . . . 11 6.3 System clock and clock options . . . . . . . . . . . 11 6 ...