AT89C51ID2-RLTUM Atmel, AT89C51ID2-RLTUM Datasheet - Page 93

IC 8051 MCU FLASH 64K 44VQFP

AT89C51ID2-RLTUM

Manufacturer Part Number
AT89C51ID2-RLTUM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ID2-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI, TWI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
44VQFP
Device Core
8051
Family Name
89C
Maximum Speed
40 MHz
Height
1.45 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
10.1 mm
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51ID2-RLTUM
Manufacturer:
ATMEL
Quantity:
13 937
Part Number:
AT89C51ID2-RLTUM
Manufacturer:
Atmel
Quantity:
10 000
Figure 35. Format and State in the Slave Transmitter Mode
Table 69. Status in Slave Transmitter Mode
93
(SSCS)
Status
Code
A8h
B0h
B8h
Reception of the
own slave address
and one or more
data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (AA=0)
AT89C51ID2
Status of the 2-wire bus and
Arbitration lost in SLA+R/W as
master; own SLA+R has been
Data byte in SSDAT has been
transmitted; NOT ACK has
received; ACK has been
received; ACK has been
Own SLA+R has been
2-wire hardware
From master to slave
From slave to master
been received
returned
returned
S
SLA
Load data byte or
Load data byte or
Load data byte or
To/from SSDAT
Load data byte
Load data byte
Load data byte
Application Software Response
R
Data
n
B0h
A8h
A
A
STA
X
X
X
X
X
X
A
To SSCON
STO
Data
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
0
0
0
0
0
0
SI
0
0
0
0
0
0
B8h
A
AA
0
1
0
1
0
1
Next Action Taken By 2-wire Software
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
Data
C8h
C0h
A
A
All 1’s
P or S
P or S
4289C–8051–11/05

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