AT89C51ID2-RLTUM Atmel, AT89C51ID2-RLTUM Datasheet - Page 105

• Manufacturer Part Number: AT89C51ID2-RLTUM
• Description: IC 8051 MCU FLASH 64K 44VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ID2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: UART, SPI, TWI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44VQFP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Status Register
(SPSTA)
105
AT89C51ID2
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
•
•
Table 80 describes the SPSTA register and explains the use of every bit in the register.
Table 80. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
Bit Number
Number
SPIF
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
SSERR
WCOL
WCOL
MODF
SPIF
Bit
Bit Mnemonic
6
-
-
SPR1
SPR0
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error Flag
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SSERR
5
Description
SPR2
0
0
0
0
1
1
1
1
MODF
4
SPR1
0
0
1
1
0
0
1
1
Table 2.
SPR0 Serial Peripheral Rate
0
1
0
1
0
1
0
1
3
-
F
F
F
F
F
F
F
Invalid
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
2
-
/2
/4
/8
/16
/32
/64
/128
1
-
4289C–8051–11/05
0
-