ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 92

MCU AVR 128K ISP FLASH 44-TQFP

ATMEGA1284P-AU

Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA1284P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Register Description
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
8272A–AVR–01/10
MCUCR – MCU Control Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
PINB – Port B Input Pins Address
Note:
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 74
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x02 (0x22)
Read/Write
Initial Value
Bit
0x01 (0x21)
Read/Write
Initial Value
Bit
0x00 (0x20)
Read/Write
Initial Value
Bit
0x05 (0x25)
Read/Write
Initial Value
Bit
0x04 (0x24)
Read/Write
Initial Value
Bit
0x03 (0x23)
Read/Write
Initial Value
1. Only available in the ATmega164PA/324PA/644PA/1284P.
PORTB7
PORTA7
PINA7
PINB7
DDB7
DDA7
JTD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
7
0
7
0
7
0
7
7
0
7
0
7
BODS
PORTA6
PORTB6
PINA6
PINB6
DDB6
DDA6
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
R
6
0
6
0
6
0
6
6
0
6
0
6
(1)
for more details about this feature.
PORTA5
PORTB5
BODSE
PINA5
PINB5
DDA5
DDB5
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
5
0
5
0
5
5
0
5
0
5
R
5
0
(1)
PORTA4
PORTB4
PINA4
PINB4
DDA4
DDB4
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
4
0
4
0
4
4
0
4
0
4
PUD
R/W
0
4
PORTA3
PORTB3
PINA3
PINB3
DDA3
DDB3
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
3
0
3
0
3
3
0
3
0
3
R
3
0
PORTA2
PORTB2
PINA2
PINB2
DDA2
DDB2
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
2
0
2
0
2
2
0
2
0
2
R
2
0
PORTA1
PORTB1
PINA1
PINB1
DDA1
DDB1
R/W
R/W
R/W
R/W
R/W
R/W
IVSEL
N/A
N/A
R/W
1
0
1
0
1
1
0
1
0
1
1
0
PORTA0
PORTB0
PINA0
PINB0
DDA0
DDB0
R/W
IVCE
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
0
0
0
0
0
0
0
0
0
0
0
0
MCUCR
PORTA
PORTB
DDRA
DDRB
PINA
PINB
”Con-
92

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