ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet
ATMEGA1284P-AU
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ATMEGA1284P-AU Summary of contents
Page 1
... Extended Standby • I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 1.8 - 5.5V for ATmega1284P • Speed Grades – MHz @ 1.8 - 5.5V – MHz @ 2.7 - 5.5V – MHz @ 4.5 - 5.5V • ...
Page 2
... Pin Configurations Figure 1-1. Note: 8059D–AVR–11/09 Pinout ATmega1284P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 ...
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... Overview The ATmega1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
Page 4
... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega1284P as listed on page 78. ...
Page 5
... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega1284P as listed on page 80. ...
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... The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc- tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 8059D–AVR–11/09 ATmega1284P 6 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8059D–AVR–11/09 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega1284P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 8
... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega1284P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 9
... Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8059D–AVR–11/ R/W R/W R/W R ⊕ V ATmega1284P R/W R/W R/W R SREG 9 ...
Page 10
... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 5-2, each register is also assigned a data memory address, mapping them ATmega1284P 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 8059D–AVR–11/09 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATmega1284P Figure 5- R26 (0x1A R28 (0x1C R30 (0x1E ...
Page 12
... RAMPZ4 R/W R/W R/W R The Z-pointer used by ELPM and SPM 7 0 RAMPZ directly generated from the selected clock source for the CPU shows the parallel instruction fetches and instruction executions enabled ATmega1284P SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 R/W ...
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... Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. ”Memory Programming” on page ATmega1284P ”Memory Program- ”Interrupts” on page 59. The list also ” ...
Page 14
... SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 8059D–AVR–11/09 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega1284P 14 ...
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... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 8059D–AVR–11/09 ; set Global Interrupt Enable ATmega1284P 15 ...
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... For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega1284P Program Counter (PC bits wide, thus addressing the 64K program memory locations. The ...
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... SRAM Data Memory Figure 6-2 The ATmega1284P is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used ...
Page 18
... The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 16K bytes of internal data SRAM in the ATmega1284P are all accessible through all these addressing modes. The Register File is described in 10. Figure 6-2. 6.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 6-3 ...
Page 19
... EEPROM Data Memory The ATmega1284P contains 4K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 20
... I/O Memory The I/O space definition of the ATmega1284P is shown in All ATmega1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 21
... Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space ...
Page 22
... EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use for details about Boot programming. ATmega1284P ”Memory Pro- 22 ...
Page 23
... The calibrated Oscillator is used to time the EEPROM accesses. typical programming time for EEPROM access from the CPU. Table 6-2. Symbol EEPROM write (from CPU) 8059D–AVR–11/09 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega1284P Table 6-2 on page 23 lists the Typ Programming Time 3 ...
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... Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); 1. See “About Code Examples” on page 6. ATmega1284P 24 ...
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... Read data from Data Register in r16,EEDR ret (1) /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “About Code Examples” on page 6. ATmega1284P 25 ...
Page 26
... R/W R/W R MSB R/W R/W R SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external). ATmega1284P R/W R/W R/W R R/W R/W R/W ...
Page 27
... ASY Source clock System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator Oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega1284P Flash and CPU Core RAM EEPROM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock Watchdog ...
Page 28
... Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t CC ATmega1284P (1) CKSEL3..0 1111 - 1000 0111 - 0110 0101 - 0100 ”On-chip Debug System” on page 44 ...
Page 29
... Figure 7-2. 8059D–AVR–11/09 Table 7-2. The frequency of the Watchdog Oscillator is voltage ”Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 Crystal Oscillator Connections C2 C1 ATmega1284P 334. = 3.0V) Number of Cycles 4.3 ms 512 (8,192) Figure 7-2 on page XTAL2 XTAL1 GND 0 29 ...
Page 30
... Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega1284P ”Clock Source Connections” on page (3) Recommended Range for Capacitors C1 and C2 (pF) (2) – 101 110 ...
Page 31
... Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega1284P Additional Delay from Reset (V = 5.0V) CKSEL0 CC 14CK 14CK + 4.1 ms 14CK + ...
Page 32
... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega1284P oscillator is optimized for very low power consumption, and thus when selecting crystals, see crystals Table 7-7 ...
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... Start-up Time from Power-down and Power-save Reserved 32K CK 32K CK 32K CK Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega1284P Figure 7-2 on page 29 Table 7-8 on page Figure 7-2 on page 29. TOSC2 TOSC1 Typ. (pF) Max. (pF) 8.0 Additional Delay from Reset ( ...
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... Start-up times for the Internal Calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved The device is shipped with this option selected. 1. ATmega1284P for more details. ”OSCCAL – Oscillator Calibration Register” on Table 26-1 on page 294. (1)(3) CKSEL3..0 0010 Additional Delay from Reset ( ...
Page 35
... Start-up Time from Power- down and Power-save Reserved External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL Crystal Oscillator Clock Frequency Nominal Frequency kHz ATmega1284P Table 7-13. CKSEL3..0 0011 Additional Delay from Reset SUT1..0 14CK 14CK + 4 ms 14CK + 64 ms XTAL2 XTAL1 GND CKSEL3..0 ...
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... System Clock Prescaler The ATmega1284P has a system clock prescaler, and the system clock can be divided by set- ting the the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 37
... Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 8059D–AVR–11/09 ATmega1284P 37 ...
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... R/W R/W R/W Device Specific Calibration Value Table 26-1 on page 326. The application software can write this register to change 326. Calibration outside that range is not guaranteed CLKPCE – – R 39. ATmega1284P CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 R R/W ...
Page 39
... The device is shipped with the CKDIV8 Fuse programmed. Table 7-17. CLKPS3 8059D–AVR–11/09 Clock Prescaler Select CLKPS2 CLKPS1 ATmega1284P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 39 ...
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... SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8059D–AVR–11/09 for more details. presents the different clock systems in the ATmega1284P, and their dis- Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains X ...
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... MCU from ADC Noise Reduction mode. 8059D–AVR–11/09 level has dropped during the sleep period. CC 46. Writing this bit to one turns off the BOD in rele- 46. and clk , while allowing the other clocks to run. CPU FLASH ATmega1284P Table 25-3 on page 292, Table 8-1 on page ”MCUCR – 41 ...
Page 42
... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 8059D–AVR–11/09 ATmega1284P ”External Interrupts” on page 65 ”Clock Sources” on page 28. ...
Page 43
... Refer to age Reference” on page 52 8059D–AVR–11/09 ”AC - Analog Comparator” on page 237 for details on the start-up time. ATmega1284P page 46, provides a method to stop the ”ADC - Analog-to-digital Converter” on page for details on how to configure the Ana- ” ...
Page 44
... Input Enable and Sleep Modes” on page 74 /2, the input buffer will use excessive power input pin can cause significant current even in active mode. Digital CC ”DIDR1 – Digital Input Disable Register 1” on page 239 for details. ATmega1284P for details on and ”DIDR0 – Digital 44 ...
Page 45
... Sleep Mode Select SM1 SM0 Standby modes are only recommended for use with external crystals or resonators. ATmega1284P – SM2 SM1 SM0 R R/W R/W R Table 8-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby 0 SE SMCR R/W ...
Page 46
... When the Timer/Counter2 is enabled, operation will continue like before the shutdown. 8059D–AVR–11/ JTD BODS BODSE R 40. Writing to the BODS bit is controlled by a timed sequence and an enable bit PRTWI PRTIM2 PRTIM0 PRUSART1 R/W R/W R/W R ATmega1284P PUD – – IVSEL R R PRTIM1 PRSPI PRUSART0 R/W ...
Page 47
... Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 8059D–AVR–11/09 ATmega1284P 47 ...
Page 48
... Reset Sources The ATmega1284P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 49
... Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] ”System and Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC ATmega1284P DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 327. The POR is activated whenever 49 ...
Page 50
... CC V RST RESET t TOUT RESET MCU Start-up, RESET Extended Externally V POT V CC RESET RESET ”System and Reset Characteristics” on page External Reset During Operation CC ATmega1284P CC V RST t TOUT 327) will generate a – on its positive edge, the RST – has expired. TOUT 50 ...
Page 51
... Brown-out Detection ATmega1284P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
Page 52
... Internal Voltage Reference ATmega1284P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
Page 53
... Overview ATmega1284P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
Page 54
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega1284P 54 ...
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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega1284P 55 ...
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... Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 8059D–AVR–11/ – – – JTRF R ATmega1284P WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description MCUSR 56 ...
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... Watchdog Timer Configuration WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode ATmega1284P WDE WDP2 WDP1 WDP0 R/W R/W R/W R Action on Time-out None Interrupt Reset Interrupt, then go to System ...
Page 58
... WDP2 WDP1 WDP0 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles ATmega1284P Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles 0.125 s Reserved = 5. 0.25 s 0.5 s 1.0 s 2.0 s 4 ...
Page 59
... Interrupts 10.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega1284P. For a general explanation of the AVR interrupt handling, refer to on page 10.2 Interrupt Vectors in ATmega1284P Table 10-1. Vector No 8059D–AVR–11/09 13. Reset and Interrupt Vectors Program (2) Address Source (1) $0000 ...
Page 60
... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 10-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega1284P is: Address 0x0000 0x0002 0x0004 0x0006 ...
Page 61
... Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx jmp EXT_INT0 ; IRQ0 Handler ATmega1284P ; Timer1 Capture ; Timer1 CompareA ; Timer1 CompareB ; Timer1 Overflow ; Timer0 CompareA ; Timer0 CompareB ; Timer0 Overflow ; SPI Transfer Complete ; USART0 RX Complete ; USART0,UDR Empty ; USART0 TX Complete ...
Page 62
... Comments jmp RESET ; Reset handler jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler ... ... ; jmp SPM_RDY ; SPM Ready Handler r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx ATmega1284P 62 ...
Page 63
... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section for details on Boot Lock bits. ATmega1284P ...
Page 64
... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); ATmega1284P 64 ...
Page 65
... Initial Value • Bits 7:6 – Reserved These bits are reserved in the ATmega1284P, and will always read as zero. • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...
Page 66
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed – – – – – – R for more information. ATmega1284P – – INT2 INT1 R R R/W R – – INTF2 INTF1 R R ...
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... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 8059D–AVR–11/ – – – – – – ATmega1284P PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R PCIF3 PCIF2 PCIF1 PCIF0 R/W R/W R/W R ...
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... PCINT30 PCINT29 PCINT28 R/W R/W R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega1284P PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W ...
Page 69
... If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8059D–AVR–11/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega1284P PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 69 ...
Page 70
... Ground as indicated in CC for a complete list of parameters. Pxn C pin ”Register Description” on page 76. Refer to the individual module sections for a full description of the alter- ATmega1284P Figure 12-1. Refer to ”Electrical Char Logic See Figure "General Digital I/O" for Details 90. ” ...
Page 71
... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 90, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega1284P Figure 12-2 PUD Q D ...
Page 72
... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega1284P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...
Page 73
... SYNC LATCH PINxn r17 Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega1284P XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
Page 74
... Figure 12-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega1284P /2. CC 76. 74 ...
Page 75
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8059D–AVR–11/09 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega1284P 75 ...
Page 76
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega1284P Figure 12-2 on page 71 PUD ...
Page 77
... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega1284P Fig- 77 ...
Page 78
... ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) ATmega1284P . 78 ...
Page 79
... PCINT3 • PCIE0 + PCINT2 • PCIE0 + ADC3D ADC2D PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT3 INPUT PCINT2 INPUT ADC3 INPUT ADC2 INPUT ATmega1284P relates the alternate functions of Port A to the 76. PA5/ADC5/ PA4/ADC4/ PCINT5 PCINT4 PCINT5 • PCIE0 + PCINT4 • PCIE0 + ADC5D ADC4D PCINT5 • ...
Page 80
... AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10) T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) ATmega1284P Table 12-6. 80 ...
Page 81
... Analog Comparator. INT2, External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to the MCU. PCINT10, Pin Change Interrupt source 10: The PB2 pin can serve as an external interrupt source. • T1/CLKO/PCINT9, Bit 1 T1, Timer/Counter1 counter source. 8059D–AVR–11/09 ATmega1284P 81 ...
Page 82
... PCINT15 • PCIE1 PCINT14 • PCIE1 1 1 SCK INPUT SPI MSTR INPUT PCINT17 INPUT PCINT14 INPUT – – ATmega1284P PB5/MOSI/ PB4/SS/OC0B/ ICP3/PCINT13 PCINT12 SPE • MSTR SPE • MSTR PORTB13 • PUD PORTB12 • PUD SPE • MSTR SPE • MSTR ...
Page 83
... TMS (JTAG Test Mode Select) PCINT19 (Pin Change Interrupt 19) TCK (JTAG Test Clock) PCINT18 (Pin Change Interrupt 18) SDA (2-wire Serial Bus Data Input/Output Line) PCINT17 (Pin Change Interrupt 17) SCL (2-wire Serial Bus Clock Line) PCINT16 (Pin Change Interrupt 16) ATmega1284P PB1/T1/CLKO/PCIN PB0/T0/XCK/ T9 PCINT8 ...
Page 84
... SCL, 2-wire Serial Busk Clock Line. PCINT23, Pin Change Interrupt source 23: The PC0 pin can serve as an external interrupt source. Table 12-10 shown in 8059D–AVR–11/09 and Table 12-11 relate the alternate functions of Port C to the overriding signals Figure 12-5 on page 76. ATmega1284P 84 ...
Page 85
... PC3/TMS/ PC2/TCK/ PCINT19 PCINT18 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN JTAGEN JTAGEN 1 1 PCINT19 INPUT PCINT18 INPUT TMS INPUT TCK INPUT ATmega1284P PC5/TDI/ PC4/TDO/ PCINT21 PCINT20 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 PCINT21 INPUT PCINT20 INPUT TDI INPUT – ...
Page 86
... TXD1 (USART1 Transmit Pin) PCINT27 (Pin Change Interrupt 27) INT0 (External Interrupt0 Input) RXD1 (USART1 Receive Pin) PCINT26 (Pin Change Interrupt 26) TXD0 (USART0 Transmit Pin) PCINT25 (Pin Change Interrupt 25) RXD0 (USART0 Receive Pin) PCINT24 (Pin Change Interrupt 24) T3 (Timer/Counter 3 External Counter Input) ATmega1284P Table 12-12. 86 ...
Page 87
... TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. PCINT27, Pin Change Interrupt Source 27: The PD3 pin can serve as an external interrupt source. 8059D–AVR–11/09 ATmega1284P 87 ...
Page 88
... OC2A ENABLE OC2B ENABLE OCA2A OC2B PCINT31 • PCIE3 PCINT30 • PCIE3 1 1 ICP1 INPUT PCINT31 INPUT PCINT30 INPUT – – ATmega1284P relates the alternate functions of Port D to PD5/OC1A/ PD4/OC1B/XCK1/ PCINT29 PCINT28 OC1A ENABLE OC1B ENABLE OC1A OC1B PCINT29 • PCIE3 PCINT28 • ...
Page 89
... When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega1284P (1) PD1/TXD0/ ...
Page 90
... PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega1284P – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 ...
Page 91
... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega1284P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 92
... Count Clear Control Logic Direction TOP BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Value = OCRnB TCCRnA TCCRnB ATmega1284P Figure 13-1. For the actual 2. CPU accessible I/O Registers, includ- TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) = 0 OCnA (Int.Req.) Waveform OCnA ...
Page 93
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ”Timer/Counter Prescaler” on page DATA BUS count clear TCNTn direction bottom ATmega1284P 153. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 94
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 97. shows a block diagram of the Output Compare unit. ATmega1284P in the following. T0 (”Modes of Operation” on page 97). ”Modes of 94 ...
Page 95
... Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 8059D–AVR–11/09 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega1284P TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 95 ...
Page 96
... The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 8059D–AVR–11/09 COMnx1 Waveform COMnx0 Generator FOCn clk I/O See Section “13.9” on page 103. ATmega1284P Figure 13-4 shows a simplified OCnx OCnx PORT ...
Page 97
... Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 8059D–AVR–11/09 Table 13-2 on page 103, and for phase correct PWM refer to 121.). ”Timer/Counter Timing Diagrams” on page ATmega1284P 103. For fast PWM mode, refer to Table 13-4 on page 104. 101. Figure 13-5. The counter value (TCNT0) ...
Page 98
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8059D–AVR–11/ clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx ATmega1284P OCnx Interrupt Flag Set (COMnx1 OC0 ) 98 = ...
Page 99
... The TCNT0 value is in the timing diagram shown as a his Table 13-3 on page 103). The actual OC0x value will only be visible ----------------- - OCnxPWM N 256 = f OC0 ATmega1284P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 clk_I/O ⋅ /2 when OCR0A is set to zero. This clk_I/O 99 ...
Page 100
... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 8059D–AVR–11/09 13-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATmega1284P OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 101
... Figure 13-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega1284P 104). The actual OC0x value will only f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 13-7 ...
Page 102
... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega1284P /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 103
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 98 for more details. shows the COM0A1:0 bit functionality when the WGM02:0 bits are set ATmega1284P COM0B0 – ...
Page 104
... A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done atBOTTOM. See 98 for more details. ATmega1284P (1) ”Phase Correct PWM Mode” on shows the COM0A1:0 bit functionality when the (1) ” ...
Page 105
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 106
... These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the 8059D–AVR–11/ FOC0A FOC0B – – ”TCCR0A – Timer/Counter Control Register A” on page ATmega1284P WGM02 CS02 CS01 CS00 R/W R/W R/W R 103. TCCR0B 106 ...
Page 107
... I clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R ATmega1284P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R TCNT0 R OCR0A R/W 0 107 ...
Page 108
... Flag Register – TIFR0. 13.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit 0x15 (0x35) Read/Write Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. 8059D–AVR–11/ OCR0B[7:0] R/W ...
Page 109
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 8059D–AVR–11/09 ATmega1284P Table 105. 13-8, ”Waveform ...
Page 110
... The PRTIM1 bit in enable Timer/Counter1 module. 8059D–AVR–11/09 ”Pin Configurations” on page ”Register Description” on page 131. ”PRR0 – Power Reduction Register 0” on page 46 ATmega1284P Figure 14-1. For the actual 2. CPU accessible I/O Registers, includ- must be written to zero to 110 ...
Page 111
... PWM or variable frequency output on the Output Compare pin (OCnA/B/C). 8059D–AVR–11/09 Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2 and pin placement and description. ATmega1284P (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 112
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega1284P (See 112 ...
Page 113
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega1284P 113 ...
Page 114
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega1284P 114 ...
Page 115
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ”Timer/Counter Prescaler” on page ATmega1284P 153. 115 ...
Page 116
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ”Modes of Operation” on page ATmega1284P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 122 ...
Page 117
... ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8059D–AVR–11/09 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega1284P Figure 14-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 118
... Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be 8059D–AVR–11/09 112. ATmega1284P ”Accessing 16-bit Registers” (Figure 14-1 on page 111). The edge detector is also ...
Page 119
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega1284P 122.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 120
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 8059D–AVR–11/09 112. ATmega1284P ”Accessing 16-bit Registers” 120 ...
Page 121
... The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 8059D–AVR–11/09 Waveform Generator I/O See Section “14.11” on page 131. ATmega1284P Figure 14 OCnx ...
Page 122
... It also simplifies the opera- tion of counting external events. 8059D–AVR–11/09 Table 14-2 on page 131. For fast PWM mode refer to 121.) ”Timer/Counter Timing Diagrams” on page ATmega1284P Table 14-3 on Table 14-4 on 129. 122 ...
Page 123
... PWM mode can be twice as high as the phase cor- 8059D–AVR–11/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega1284P Figure 14-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 123 ...
Page 124
... The ICRn Register is not double buffered. This means that if ICRn is changed to a low 8059D–AVR–11/09 ( log TOP R = ---------------------------------- - FPWM log ATmega1284P ) Figure 14-7. The figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 125
... In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope 8059D–AVR–11/09 Table on page f clk_I ---------------------------------- - ⋅ ( OCnxPWM TOP = f /2 when OCRnA is set to zero (0x0000). This feature clk_I/O ATmega1284P 132). The actual OCnx ) 125 ...
Page 126
... Note that when using fixed TOP values, the unused bits are masked to zero when any of the 8059D–AVR–11/ log TOP + ---------------------------------- - PCPWM log ATmega1284P Figure 14-8. The figure OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 126 ...
Page 127
... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 8059D–AVR–11/09 f OCnxPCPWM 14-9). ATmega1284P Figure 14-8 illustrates, changing the Table on page f clk_I/O = --------------------------- - ⋅ ...
Page 128
... R = ---------------------------------- - PFCPWM Figure 14-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega1284P ( ) 1 TOP + log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 129
... OCnxPFCPWM Figure 14-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega1284P f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value Table on ...
Page 130
... I/O TCNTn TOP - 1 TCNTn TOP - 1 TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega1284P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 ...
Page 131
... OCRnx Old OCRnx Value (Update at TOP COMnA1 COMnA0 COMnB1 R/W R/W R Table 14-2 on page 131 Compare Output Mode, non-PWM COMnA0/COMnB0 ATmega1284P /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COMnB0 – – WGMn1 R R shows the COMnx1:0 bit functionality Description Normal port operation, OCnA/OCnB disconnected. ...
Page 132
... A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. Section “14.9.4” on page 125. for more details. Table 14-5 on page ATmega1284P (1) Description Normal port operation, OCnA/OCnB disconnected. WGMn3 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 133
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNCn ICESn – WGMn3 R/W R ATmega1284P Update of x TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICRn BOTTOM OCRnA BOTTOM ICRn ...
Page 134
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOCnA FOCnB – R/W R ATmega1284P – – – – Figure 0 – TCCRnC R 0 134 ...
Page 135
... TCNTn[15:8] TCNTn[7:0] R/W R/W R/W R OCRnA[15:8] OCRnA[7:0] R/W R/W R/W R OCRnB[15:8] OCRnB[7:0] R/W R/W R/W R See Section “14.3” on page 112. ATmega1284P R/W R/W R/W R See Section “14.3” R/W R/W R/W R R/W R/W R/W R TCNTnH TCNTnL OCRnAH OCRnAL OCRnBH OCRnBL ...
Page 136
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega1284P, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 137
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega1284P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 138
... ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. • Bit 4:3 – Res: Reserved Bits These bits are unused bits in the ATmega1284P, and will always read as zero. 8059D–AVR–11/09 7 ...
Page 139
... TOV3 Flag is set when the timer overflows. Refer to Flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. 8059D–AVR–11/09 ATmega1284P Table 14-5 on page 133 for the TOV3 139 ...
Page 140
... BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Value = OCRnB Synchronized Status flags asynchronous mode Status flags ASSRn TCCRnA TCCRnB ATmega1284P 2. CPU accessible I/O Registers, includ- 153. ”PRR0 – Power Reduction Register 0” on TOVn (Int.Req.) clk Tn T/C Oscillator Prescaler clk I OCnA (Int.Req.) Waveform ...
Page 141
... OCR2A Register. The assignment is depen- dent on the mode of operation default equal to the MCU clock, clk T2 153. ATmega1284P for details. The compare match event will also set the 158. For details on clock sources and prescaler, see . When the AS2 I/O ” ...
Page 142
... Signalizes that TCNT2 has reached maximum value. Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 145. ATmega1284P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk top in the following ...
Page 143
... TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 8059D–AVR–11/09 shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega1284P (”Modes of Operation” on page TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 145). 143 ...
Page 144
... Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction 8059D–AVR–11/09 Waveform Generator clk I/O ATmega1284P Figure 15-4 shows a simplified OCnx ...
Page 145
... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 8059D–AVR–11/09 ”Register Description” on page 153. Table 15-5 on page 155. For fast PWM mode, refer to Table 15-7 on page 144.). ”Timer/Counter Timing Diagrams” on page ATmega1284P Table 15-6 on 155. 149. 145 ...
Page 146
... This high frequency makes the fast PWM mode well suited 8059D–AVR–11/09 Table 15-5 on page clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx Flag is set in the same timer clock cycle that the TOV2 ATmega1284P 146. The counter value OCnx Interrupt Flag Set (COMnx1 OC2A ) 146 = ...
Page 147
... Figure 15-6 on page 147. The TCNT2 value is in the timing diagram Table 15-3 on page f clk_I ----------------- - OCnxPWM N 256 ATmega1284P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 154). The actual OC2x value will only ⋅ 147 ...
Page 148
... Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 8059D–AVR–11/09 15-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating 1 ATmega1284P = f /2 when OCR2A is set to zero. This fea- oc2 clk_I/O OCnx Interrupt Flag Set ...
Page 149
... Table 15-4 on page f clk_I ----------------- - ⋅ OCnxPCPWM N 510 Figure 15-7 on page 148 OCnx has a transition from high to low Figure 15-7 on page contains timing data for basic Timer/Counter operation. The figure ATmega1284P 154). The actual OC2x 148. When the OCR2A value ) T2 should be replaced by I/O 149 ...
Page 150
... I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode. clk I/O clk Tn /8) I/O OCRnx - 1 ATmega1284P MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value BOTTOM + 1 BOTTOM + 1 /8) clk_I/O ...
Page 151
... OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode 8059D–AVR–11/09 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn /8) I/O TOP - 1 Enable interrupts, if needed. ATmega1284P TOP BOTTOM BOTTOM + 1 TOP 151 ...
Page 152
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8059D–AVR–11/09 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega1284P 152 ...
Page 153
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S COM2A1 COM2A0 COM2B1 R/W R/W R ATmega1284P 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S for details. /8, clk T2S as well as 0 (stop) may be selected. T2S ...
Page 154
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 148 for more details. ATmega1284P (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...
Page 155
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. 8059D–AVR–11/09 Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected ...
Page 156
... Reserved PWM, Phase Correct Reserved Fast PWM 1. MAX= 0xFF 2. BOTTOM= 0x00 FOC2A FOC2B – ATmega1284P ”Modes of Operation” on page 145). Update of TOP OCRx at 0xFF Immediate 0xFF TOP OCRA Immediate 0xFF BOTTOM – – OCRA TOP – – OCRA BOTTOM – WGM22 ...
Page 157
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega1284P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select ...
Page 158
... A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. 8059D–AVR–11/ OCR2A[7:0] R/W R/W R/W R OCR2B[7:0] R/W R/W R/W R – EXCLK AS2 TCN2UB OCR2AUB R R/W R ATmega1284P R/W R/W R/W R R/W R/W R/W R OCR2BUB TCR2AUB TCR2BUB When AS2 is I/O OCR2A OCR2B 0 ASSR R 0 ...
Page 159
... Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 8059D–AVR–11/ – – – – ATmega1284P – OCIE2B OCIE2A TOIE2 R R/W R/W R TIMSK2 159 ...
Page 160
... TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn- chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode. 8059D–AVR–11/ – – – – TSM – – – R ATmega1284P – OCF2B OCF2A TOV2 R R/W R/W R – – PSRASY PSRSYNC R R R/W R TIFR2 GTCCR ...
Page 161
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega1284P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 198. The Power Reduction SPI bit, PRSPI, in page 50 must be written to zero to enable SPI module ...
Page 162
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 8059D–AVR–11/09 ATmega1284P Figure 16-2. The sys- SHIFT ENABLE ...
Page 163
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See ”Alternate Functions of Port B” on page 80 direction of the user defined SPI pins. ATmega1284P ”Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 163 ...
Page 164
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 6. ATmega1284P 164 ...
Page 165
... Read received data and return r16,SPDR in ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “About Code Examples” on page 6. ATmega1284P 165 ...
Page 166
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 16-2 on page 167 8059D–AVR–11/09 and Figure 16-4 on page 167. Data bits are shifted out and latched in on Table 16-3 on page 168 ATmega1284P and Table 16-4 on page 168, as done in Figure 166 ...
Page 167
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega1284P Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 168
... Figure 16-3 and Figure 16-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 16-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega1284P CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 16-4 for an example ...
Page 169
... Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega1284P is also used for program memory and EEPROM down- loading or uploading. See 8059D–AVR–11/09 Relationship Between SCK and the Oscillator Frequency ...
Page 170
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8059D–AVR–11/ MSB R/W R/W R/W R ATmega1284P LSB R/W R/W R/W R SPDR Undefined 170 ...
Page 171
... USART1 and USART0 The ATmega1284P has two USART’s, USART0 and USART1. The functionality for all USART’s is described below, most register and bit references in this sec- tion are written in general form. A lower case “n” replaces the USART number. ...
Page 172
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. See Figure 1-1 on page 2 and ”Alternate Port Functions” on page 76 placement. ATmega1284P Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 173
... Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and 1. The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) ATmega1284P U2X / ...
Page 174
... OSC BAUD = ----------------------------------------- - ( 16 UBRRn f OSC BAUD = -------------------------------------- - ( 8 UBRRn f OSC BAUD = -------------------------------------- - ( 2 UBRRn System Oscillator clock frequency Contents of the UBRRHn and UBRRLn Registers, (0-4095) Figure 17-2 on page 173 for details. ATmega1284P Equation for Calculating UBRR Value f OSC ----------------------- - 1 UBRRn = – 16BAUD ) OSC ------------------- - 1 UBRRn = – 8BAUD ) OSC ...
Page 175
... It is therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 17-3 on page 175 illustrates the possible combinations of the frame formats. Bits inside ATmega1284P f OSC < ---------- - f XCK 4 Sample Sample shows, when UCPOLn is zero the data will ...
Page 176
... No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. ⊕ even – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega1284P FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 177
... UCSRnC,r16 ret (1) /* Set baud rate */ UBRRHn = (unsigned char)(baud>>8); UBRRLn = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); 1. See “About Code Examples” on page 6. ATmega1284P 177 ...
Page 178
... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “About Code Examples” on page 6. ATmega1284P 178 ...
Page 179
... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See “About Code Examples” on page 6. ATmega1284P 179 ...
Page 180
... The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. 8059D–AVR–11/09 ATmega1284P 180 ...
Page 181
... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “About Code Examples” on page 6. ATmega1284P 181 ...
Page 182
... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 6. ATmega1284P 182 ...
Page 183
... Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together 8059D–AVR–11/09 ”Parity Bit Calculation” on page 176 ATmega1284P and ”Parity Checker” on page 183. ...
Page 184
... Note the 8059D–AVR–11/09 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 6. ATmega1284P Figure 17-5 184 ...
Page 185
... Figure 17-7 on page 186 of the start bit of the next frame. 8059D–AVR–11/09 RxD IDLE RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning ATmega1284P START Figure 17-6 shows the sampling of the data bits and BIT ...
Page 186
... Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 17-3 on page 187 ATmega1284P STOP 1 (A) ( ...
Page 187
... ATmega1284P Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± 1.5 ...
Page 188
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 8059D–AVR–11/09 ATmega1284P 188 ...
Page 189
... The UDREn Flag can generate a 8059D–AVR–11/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega1284P R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA ...
Page 190
... TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 8059D–AVR–11/09 ”Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega1284P 187 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 190 ...
Page 191
... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn Bits Settings UMSELn0 See ”USART in SPI Mode” on page 198 operation ATmega1284P UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 17-4.. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) ...
Page 192
... UPMn Bits Settings UPMn1 UPMn0 USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit UCSZn Bits Settings UCSZn1 ATmega1284P Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 192 ...
Page 193
... Transmitted Data Changed (Output of TxDn Pin) Rising XCKn Edge Falling XCKn Edge – – – – UBRR[7: R/W R/W R/W R ATmega1284P Received Data Sampled (Input on RxDn Pin) Falling XCKn Edge Rising XCKn Edge UBRR[11: R/W R/W R/W R/W R/W R/W R/W R UBRRHn UBRRLn 193 ...
Page 194
... ATmega1284P Table 17-9 ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2Xn = 1 U2Xn = 0 UBRR Error UBRR Error 95 0. ...
Page 195
... Mbps ATmega1284P f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
Page 196
... Mbps 691.2 kbps ATmega1284P MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 197
... Mbps 1.152 Mbps ATmega1284P f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
Page 198
... Note: 8059D–AVR–11/09 Table 18-1: Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate BAUD = -------------------------------------- - ( 2 UBRRn 1. The baud rate is defined to be the transfer rate in bit per second (bps) ATmega1284P Equation for Calculating UBRRn (1) Value f OSC UBRRn = ) OSC ------------------- - 1 – ...
Page 199
... UCPOL=0 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) ATmega1284P Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising) UCPOL=1 XCK Data setup (TXD) ...
Page 200
... Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since UBRRn is reset to zero. ATmega1284P 200 ...