ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 306

• Manufacturer Part Number: ATMEGA1284P-AU
• Description: MCU AVR 128K ISP FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Rom Size: 4 KB
• Height: 1.05 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 10.1 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.9
26.7.10
26.7.11
8272A–AVR–01/10
Programming the Fuse High Bits
Programming the Extended Fuse Bits
Programming the Lock Bits
The algorithm for programming the Fuse High bits is as follows (refer to
Flash” on page 302
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS2, BS1 to “01”. This selects high data byte.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS2, BS1 to “00”. This selects low data byte.
The algorithm for programming the Extended Fuse bits is as follows (refer to
Flash” on page 302
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS2, BS1 to “10”. This selects extended data byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2, BS1 to “00”. This selects low data byte.
Figure 26-5. Programming the FUSES Waveforms
The algorithm for programming the Lock bits is as follows (refer to
page 302
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
RESET +12V
RDY/BSY
PAGEL
XTAL1
DATA
for details on Command and Data loading):
XA1
XA0
BS1
BS2
WR
OE
0x40
A
for details on Command and Data loading):
for details on Command and Data loading):
DATA
C
Write Fuse Low byte
XX
0x40
A
DATA
C
Write Fuse high byte
XX
”Programming the Flash” on
0x40
A
DATA
C
Write Extended Fuse byte
”Programming the
”Programming the
XX
306