ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 323

• Manufacturer Part Number: ATMEGA1284P-AU
• Description: MCU AVR 128K ISP FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Rom Size: 4 KB
• Height: 1.05 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 10.1 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.10.12 Programming Algorithm
26.10.13 Entering Programming Mode
26.10.14 Leaving Programming Mode
8272A–AVR–01/10
ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is
post-incremented after reading each high byte, including the first read byte. This ensures that
the first data is captured from the first address set up by PROG_COMMANDS, and reading the
last location in the page makes the program counter increment into the next page.
Figure 26-17. Flash Data Byte Register
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal
operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate
through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-
ter with sufficient number of clock pulses to complete its operation transparently for the user.
However, if too few bits are shifted between each Update-DR state during page load, the TAP
controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at
least 11 TCK cycles between each Update-DR state.
All references below of type “1a”, “1b”, and so on, refer to
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
ming Enable Register.
ming Enable Register.
TDO
TDI
D
A
A
T
Machine
State
STROBES
ADDRESS
Table 26-18 on page
EEPROM
Lock Bits
Fuses
Flash
319.
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