ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 336

• Manufacturer Part Number: ATMEGA1284P-AU
• Description: MCU AVR 128K ISP FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1284P-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Rom Size: 4 KB
• Height: 1.05 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 10.1 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6
8272A–AVR–01/10
SPI Timing Characteristics
See
Table 27-15. SPI Timing Parameters
Note:
Figure 27-3. SPI Interface Timing Requirements (Master Mode)
164A/164PA/324A/324PA/644A/644PA/1284/1284P
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 27-3 on page 336
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
MISO
MOSI
SS high to tri-state
SCK
SCK
SCK to out high
SCK to SS high
SCK high/low
SS low to SCK
SS
Rise/Fall time
Rise/Fall time
SCK high/low
SS low to out
Description
CLCL
CLCL
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
Setup
Setup
Hold
Hold
for f
for f
CK
CK
< 12 MHz
> 12 MHz
6
4
(1)
MSB
5
MSB
and
Figure 27-4 on page 337
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
7
...
4 • t
2 • t
...
Min
10
t
20
20
ck
ck
ck
for details.
See
50% duty cycle
2
0.5 • t
Table 17-5
Typ
3.6
10
10
15
10
10
15
10
LSB
1
sck
LSB
2
3
Max
1600
8
ns
336