AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 443
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 443 of 692
- Download datasheet (11Mb)
• KILLBK: Kill IN Bank
• NBUSYBKE: Number of Busy Banks Interrupt Enable
• SHORTPACKETE: Short Packet Interrupt Enable
• STALLEDE: STALLed Interrupt Enable
• CRCERRE: CRC Error Interrupt Enable
• OVERFE: Overflow Interrupt Enable
• NAKINE: NAKed IN Interrupt Enable
• NAKOUTE: NAKed OUT Interrupt Enable
• RXSTPE: Received SETUP Interrupt Enable
• UNDERFE: Underflow Interrupt Enable
• RXOUTE: Received OUT Data Interrupt Enable
• TXINE: Transmitted IN Data Interrupt Enable
32059K–03/2011
This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
For OUT endpoints:
This bit is set when the current bank is full, at the same time as RXOUTI.
This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.
This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared by hardware after the completion of the “kill packet procedure”.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :
If the bank is really killed, the NBUSYBK field is decremented.
If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
can occur if at the same time an IN token is coming and the user wants to kill this bank.
Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while
the last bank is killed.
This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt
(NBUSYBK).
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt
(SHORTPACKET).
This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).
This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).
This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).
This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).
This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).
This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).
This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).
AT32UC3B
443
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