AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 347
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 347 of 692
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32059K–03/2011
RI: Image of RI Input
CTSIC: Clear to Send Input Change Flag
DCDIC: Data Carrier Detect Input Change Flag
DSRIC: Data Set Ready Input Change Flag
RIIC: Ring Indicator Input Change Flag
NACK: Non Acknowledge
RXBUFF: Reception Buffer Full
ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
TXEMPTY: Transmitter Empty
TIMEOUT: Receiver Time-out
PARE: Parity Error
FRAME: Framing Error
OVRE: Overrun Error
RXBRK: Break Received/End of Break
TXRDY: Transmitter Ready
0: RI is at 0.
1: RI is at 1.
0: No input change has been detected on the CTS pin since the last read of CSR.
1: At least one input change has been detected on the CTS pin since the last read of CSR.
0: No input change has been detected on the DCD pin since the last read of CSR.
1: At least one input change has been detected on the DCD pin since the last read of CSR.
0: No input change has been detected on the DSR pin since the last read of CSR.
1: At least one input change has been detected on the DSR pin since the last read of CSR.
0: No input change has been detected on the RI pin since the last read of CSR.
1: At least one input change has been detected on the RI pin since the last read of CSR.
0: No Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
0: The signal Buffer Full from the Receive Peripheral DMA Controller channel is inactive.
1: The signal Buffer Full from the Receive Peripheral DMA Controller channel is active.
If USART does not operate in SPI Slave Mode (MODE … 0xF):
ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA.
If USART operates in SPI Slave Mode (MODE = 0xF):
UNRE = 0: No SPI underrun error has occurred since the last RSTSTA.
UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA.
0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in THR, nor in the Transmit Shift Register.
0: There has not been a time-out since the last Start Time-out command (STTTO in CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in CR).
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
1: There is no character in the THR.
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
AT32UC3B
347
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