AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 432
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 432 of 692
- Download datasheet (11Mb)
22.8.2.8
Register Name:
Access Type:
Offset:
Reset Value:
• EPRSTn: Endpoint n Reset
• EPENn: Endpoint n Enable
32059K–03/2011
31
23
15
7
-
-
-
-
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
Endpoint Enable/Reset Register
EPRST6
EPEN6
30
22
14
6
-
-
UERST
Read/Write
0x001C
0x00000000
EPRST5
EPEN5
29
21
13
5
-
-
EPRST4
EPEN4
28
20
12
4
-
-
EPRST3
EPEN3
27
19
11
3
-
-
EPRST2
EPEN2
26
18
10
2
-
-
EPRST1
EPEN1
25
17
9
1
-
-
AT32UC3B
EPRST0
EPEN0
24
16
8
0
-
-
432
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