AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 401
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 401 of 692
- Download datasheet (11Mb)
32059K–03/2011
•Programming example for multi-block dma transfer : run and link at end of buffer
•Programming example for multi-block dma transfer : load next descriptor now
The idea is to run first a single block transfer followed automatically by a linked list of DMA. The
following sequence may be used:
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or
multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
q u e n c e ,
UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-
CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if
there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when
the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the
UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be
loaded.
Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-
AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the
memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-
TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received
OUT data packet).
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
The idea is to directly run first a linked list of DMA. The following sequence may be used: The
following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
• Write the starting destination address in the UDDMAnADDR register.
• Program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 4 as shown in
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in
for this endpoint in the UECFGn register to handle multiple OUT packet.
t h e
U D D M A n S T A T U S . C H E N
Figure 22-6 on page
b i t
i s
449.
a l s o
Figure 22-6 on page
Figure 22-6 on page
c l e a r e d ,
AT32UC3B
a n d
449.
449.
401
t h e
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