AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 392
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 392 of 692
- Download datasheet (11Mb)
22.7.3.7
32059K–03/2011
Address setup
The algorithm represented on
pipe.
Figure 22-24. Pipe Activation Algorithm
As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not
send packets to the device through this pipe.
The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct com-
pared to their maximal allowed values for the pipe (see
maximal FIFO size (i.e. the DPRAM size).
See
Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ
fields can be written by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the
default control pipe with this size parameter.
Once the device has answered the first host requests with the default device address 0, the host
assigns a new address to the device. The host controller has to send an USB reset to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once this SETUP transaction is over, the user writes the new address into the USB Host
Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All
following requests, on all pipes, will be performed using this new address.
When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the
following host requests will be performed using the default device address 0.
Section 22.7.1.6
Pipe Activated
Yes
CFGOK ==
Activation
PENn = 1
UPCFGn
PEPNUM
PTOKEN
INTFRQ
ALLOC
PTYPE
PSIZE
Pipe
for more details about DPRAM management.
PBK
1?
Figure 22-24 on page 392
No
ERROR
Enable the pipe.
Configure the pipe:
Allocate the configured DPRAM banks.
Test if the pipe configuration is
correct.
- interrupt request frequency
- endpoint number
- type
- size
- number of banks
must be followed in order to activate a
Table 22-1 on page
AT32UC3B
362) and to the
392
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