AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 252
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 252 of 692
- Download datasheet (11Mb)
19.14.6
Name:
Access:
Offset:
Reset Value: 0x0000F009
• EOSACC: End Of Slave Access (clear on read)
• SCLWS: Clock Wait State (automatically set / reset)
• ARBLST: Arbitration Lost (clear on read)
• NACK: Not Acknowledged (clear on read)
• OVRE: Overrun Error (clear on read)
• GACC: General Call Access (clear on read)
32059K–03/2011
31
23
15
–
–
–
7
–
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. THR / RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in
This bit is only used in Master mode.
0 = Arbitration won.
1 = Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill THR
even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
This bit is only used in Slave mode.
0 = RHR has not been loaded while RXRDY was set
1 = RHR has been loaded while RXRDY was set. Reset by read in SR when TXCOMP is set.
This bit is only used in Slave mode.
0 = No General Call has been detected.
Status Register
SR
Read-only
0x20
OVRE
30
22
14
–
–
–
6
GACC
29
21
13
–
–
–
5
Figure 19-27 on page 241
Figure 19-29 on page 243
SVACC
28
20
12
–
–
–
4
and
and
EOSACC
SVREAD
Figure 19-28 on page
Figure 19-30 on page 243
27
19
11
–
–
3
SCLWS
TXRDY
26
18
10
–
–
2
242.
ARBLST
RXRDY
25
17
–
–
9
1
AT32UC3B
TXCOMP
NACK
24
16
–
–
8
0
252
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