PIC16C765-I/P Microchip Technology, PIC16C765-I/P Datasheet - Page 54

• Manufacturer Part Number: PIC16C765-I/P
• Description: IC MCU OTP 8KX14 USB 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C765-I/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q975613

PIC16C745/765
9.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
9.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
9.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
9.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the TMR1
register pair. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
DS41124C-page 54
RC2/CCP1
Pin
Note:
Special event trigger will:
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Q
Special Event Trigger
COMPARE MODE OPERATION
BLOCK DIAGRAM
R
S
CCP1CON<3:0>
Mode Select
Output
Logic
(PIR1<2>)
Set flag bit CCP1IF
match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
Preliminary
The special event trigger output of CCP2 starts an A/D
conversion (if the A/D module is on) and resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
9.3
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
FIGURE 9-3:
A PWM output (Figure 9-4) has a time base (period) and
a time that the output stays high (duty cycle). The fre-
quency of the PWM is the inverse of the period (1/period).
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
Note:
Note:
CCPR1H (Slave)
Duty Cycle Registers
Comparator
CCPR1L
TMR2
PR2
Comparator
or 2 bits of the prescaler to create 10-bit time base.
PWM Mode (PWM)
The special event trigger from
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
(Note 1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer,
CCP1 pin and
latch D.C.
2000 Microchip Technology Inc.
CCP1CON<5:4>
R
S
Q
TRISC
<2>
RC2/CCP1
the