PIC16C765-I/P Microchip Technology, PIC16C765-I/P Datasheet - Page 18

• Manufacturer Part Number: PIC16C765-I/P
• Description: IC MCU OTP 8KX14 USB 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C765-I/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q975613

PIC16C745/765
TABLE 4-1:
DS41124C-page 18
Address
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1:
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Bank 1
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADCON1
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
Name
(3)
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
(4)
(4)
(3)
(1,3)
(3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
TRISC7
RBPU
CSRC
Bit 7
IRP
GIE
IBF
—
—
—
—
—
(4)
INTEDG
TRISC8
PEIE
ADIE
Bit 6
RP1
OBF
TX9
—
—
—
—
—
PORTA Data Direction Register
T0CS
TXEN
IBOV
RCIE
Bit 5
T0IE
RP0
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
Preliminary
SYNC
T0SE
INTE
TXIE
Bit 4
TO
—
—
—
—
USBIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
—
PORTE Data Direction Bits
TRISC2
CCP1IE
PCFG2
BRGH
Bit 2
PS2
T0IF
—
—
Z
TMR2IE
TRISC1
PCFG1
TRMT
Bit 1
INTF
POR
PS1
DC
—
2000 Microchip Technology Inc.
TRISC0
TMR1IE
CCP2IE
PCFG0
TX9D
Bit 0
RBIF
BOR
PS0
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
11-- -111 11-- -111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 -010 0000 -010
0000 0000 0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(2)
—
—
—
—
—
—
—
—
—
—
—
—
—