PIC16C765-I/P Microchip Technology, PIC16C765-I/P Datasheet - Page 17

• Manufacturer Part Number: PIC16C765-I/P
• Description: IC MCU OTP 8KX14 USB 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C765-I/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q975613

4.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1:
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Bank 0
2000 Microchip Technology Inc.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
SPECIAL FUNCTION REGISTERS
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
Name
(3)
(3)
—
—
(3)
(4)
(4)
(1,3)
(3)
(3)
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTD Data Latch when written: PORTD pins when read
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
Unimplemented
Unimplemented
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
A/D Result Register
PSPIF
ADCS1
SPEN
IRP
Bit 7
RC7
GIE
—
—
—
—
—
—
—
—
(2)
(4)
TOUTPS3
ADCS0
RP1
ADIF
Bit 6
PEIE
RC6
RX9
—
—
—
—
—
—
—
(2)
PORTA Data Latch when written: PORTA pins when read
TOUTPS2
T1CKPS1
DC1B1
DC2B1
SREN
CHS2
RCIF
Bit 5
T0IE
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
TOUTPS1
T1CKPS0
Preliminary
DC1B0
DC2B1
CREN
CHS1
INTE
Bit 4
TXIF
TO
—
—
–
T1OSCEN
TOUTPS0
CCP1M3
CCP2M3
USBIF
CHS0
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
RBIE
Bit 3
PD
—
—
—
—
GO/DONE
TMR2ON
CCP1M2
CCP2M2
T1SYNC
CCP1IF
FERR
Bit 2
RC2
RE2
T0IF
—
Z
PIC16C745/765
T2CKPS1
TMR1CS
CCP1M1
CCP2M1
TMR2IF
OERR
INTF
Bit 1
RC1
RE1
DC
—
—
T2CKPS0 -000 0000 -000 0000
TMR1ON
CCP1M0
CCP2M0
TMR1IF
CCP2IF
ADON
RX9D
Bit 0
RBIF
RC0
RE0
C
DS41124C-page 17
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xx-- -xxx uu-- -uuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
Value on:
POR,
BOR
—
—
other resets
Value on all
(2)
—
—