PIC16C765-I/P Microchip Technology, PIC16C765-I/P Datasheet - Page 107

• Manufacturer Part Number: PIC16C765-I/P
• Description: IC MCU OTP 8KX14 USB 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C765-I/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q975613

13.6
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
2000 Microchip Technology Inc.
Note:
Interrupts
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
Preliminary
LOOP BCF
Note:
BTFSC INTCON, GIE
GOTO
If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be re-
enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
2.
3.
Perform the following to ensure that inter-
rupts are globally disabled:
:
PIC16C745/765
INTCON, GIE
LOOP
An instruction clears the GIE bit while
an interrupt is acknowledged.
The program branches to the inter-
rupt vector and executes the Interrupt
Service Routine.
The Interrupt Service Routine com-
pletes the execution of the RETFIE
instruction. This causes the GIE bit to
be set (enables interrupts), and the
program returns to the instruction
after the one which was meant to dis-
able interrupts.
; Disable global
;
; Global interrupt
;
; NO, try again
;
;
;
DS41124C-page 107
interrupt bit
disabled?
Yes, continue
with program
flow