C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 463

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

SFR Definition 32.13. TMR3CN: Timer 3 Control
SFR Page = 0x0; SFR Address = 0x91
Name
Reset
Bit
1:0 T3XCLK[1:0] Timer 3 External Clock Select.
Type
7
6
5
4
3
2
Bit
T3SPLIT
TF3CEN
TF3LEN
Name
TF3H
TF3L
TR3
TF3H
R/W
7
0
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
Timer 3 SmaRTClock/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is SmaRTClock.
01: External Clock is External Oscillator/8. Capture trigger is SmaRTClock.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is SmaRTClock. Capture trigger is External Oscillator/8.
TF3L
R/W
6
0
TF3LEN
R/W
5
0
TF3CEN
R/W
Rev. 0.5
4
0
Function
T3SPLIT
R/W
3
0
TR3
R/W
2
0
C8051F96x
1
0
T3XCLK[1:0]
R/W
0
0
463