C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 158

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte
SFR Page = 0x2; SFR Address = 0xCD
SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte
SFR Page = 0x2; SFR Address = 0xCC
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Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Bit
7:2
1:0
Bit
7:0
Name
Reset
Name
Reset
Type
Type
Bit
Bit
NAOH[1:0]
NACL[7:0]
Unused
Name
Name
R
7
0
7
0
R
6
0
6
0
Read = 0b, Write = Don’t Care
Memory Address Offset High Byte.
Sets the high byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Memory Address Offset Low Byte.
Sets the low byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
R
5
0
5
0
Rev. 0.5
R
4
0
4
0
NACL[7:0]
R/W
Function
Function
R
3
0
3
0
R
2
0
2
0
1
0
1
0
NAOH[1:0]
R/W
0
0
0
0