C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 259

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “22.6. PCA Watchdog Timer
Reset” on page 283 for more information on the use and configuration of the WDT.
19.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep, Suspend, or
Low Power Idle mode will provide more power savings if the MCU needs to be inactive for a long period of
time.
19.4. Low Power Idle Mode
Low Power Idle Mode uses clock gating to reduce the supply current when the device is placed in Idle
mode. This mode is enabled by configuring the clock tree gates using the PCLKEN register, setting the
LPMEN bit in the CLKMODE register, and placing the device in Idle mode. The clock is automatically gated
from the CPU upon entry into Idle mode when the LPMEN bit is set. This mode provides substantial power
savings over the standard Idle Mode especially at high system clock frequencies.
The clock gating logic may also be used to reduce power when executing code. Low Power Active Mode is
enabled by configuring the PCLKACT and PCLKEN registers, then setting the LPMEN bit. The PCLKACT
register provides the ability to override the PCLKEN setting to force a clock to certain peripherals in Low
Power Active mode. If the PCLKACT register is left at its default value, then PCLKEN determines which
perpherals will be clocked in this mode. The CPU is always clocked in Low Power Active Mode.
CPU
Figure 19.2. Clock Tree Distribution
System
Clock
Rev. 0.5
Pulse Counter
SmaRTClock
Timer 0, 1, 2
Timer 3
UART0
SMBus
PMU0
CRC0
ADC0
PCA0
SPI0
C8051F96x
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