C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 306

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
Internal Register Definition 24.4. RTC0CN: SmaRTClock Control
SmaRTClock Address = 0x04
306
Name
Reset
Type
Bit
7
6
5
4
3
2
1
0
Bit
RTC0CAP SmaRTClock Timer Capture.
RTC0SET SmaRTClock Timer Set.
HSMODE High Speed Mode Enable.
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Reserved Read = 0b; Must write 0b.
MCLKEN Missing SmaRTClock Detector Enable.
RTC0EN SmaRTClock Enable.
RTC0TR SmaRTClock Timer Run Control.
Name
RTC0EN
R/W
7
0
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock 
oscillator is disabled.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
Should be set to 1 if the system clock is faster than 4x the SmaRTClock frequency.
0: High Speed Mode is disabled.
1: High Speed Mode is enabled.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
MCLKEN
R/W
6
0
OSCFAIL
Varies
R/W
5
RTC0TR
R/W
Rev. 0.5
4
0
Function
R/W
3
0
HSMODE RTC0SET RTC0CAP
R/W
2
0
R/W
1
0
R/W
0
0