C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 432

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
31.6. Using SPI1 with the DMA
SPI1 is a DMA-enabled peripheral that can provide autonomous data transfers when used with the DMA.
The DMA-enabled SPI1 supports both master and slave mode. The SPI requires two DMA channels for a
bidirectional data transfer and also supports unidirectional data transfers using a single DMA channel.
There are no additional control bits in the SPI1 control and configuration SFRs. The configuration is the
same in DMA and non-DMA mode. While the SPIF flag and/or SPI interrupts are normally used for non-
DMA SPI transfers, a DMA transfer is managed using the DMA enable and DMA full transfer complete
flags.
More information on using the SPI1 peripheral can be found in the detailed example code for SPI1 Master
and Slave modes.
31.7. Master Mode SPI1 DMA Transfers
The SPI interface does not normally have any handshaking or flow control. Therefore, the Master will
transmit all of the output data without waiting on the slave peripheral. The system designer must ensure
that the slave peripheral can accept all of the data at the transfer rate.
31.8. Master Mode Bidirectional Data Transfer
A bidirectional SPI Master Mode DMA transfer will transmit a specified number of bytes out on the MOSI
pin and receive the same number of bytes on the MISO pin. The MOSI data must be stored in XRAM
before initiating the DMA transfers. The DMA will also transfer all the MISO data to XRAM, overwriting any
data at the target location.
A bidirectional transfer requires two DMA channels. The first DMA channel transfers data from XRAM to
the SPI1DAT SFR and the second DMA channel transfers data from the SPI1DAT SFR to XRAM. The sec-
ond channel DMA interrupt indicates SPI transfer completion.
In master mode, the NSS pin is an output and the hardware does not manage the NSS pin automatically.
Normally, firmware should assert the NSS pin before the SPI transfer and deassert it upon completion of
the transfer. When using 4-wire Master mode, bit 2 of SPI1CN controls the state of the NSS pin. When
using 3-wire master mode, firmware may use any GPIO pin as NSS.
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