C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 166

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control
SFR Page = 0xF; SFR Address = 0x96
SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count
SFR Page = 0xF; SFR Address = 0x97
166
Name
Reset
Name
Reset
5:0
7:6
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
Bit
Bit
Type
Type
7
6
Bit
Bit
CRC0ST[5:0]
CRCDONE
AUTOEN
AUTOEN
Unused
Name
Name
7
0
7
0
CRCDONE
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at flash sector CRC0ST and continuing for CRC0CNT sectors.
CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return 1.
Automatic CRC Calculation Starting Flash Sector.
These bits specify the flash sector to start the automatic CRC calculation. The
starting address of the first flash sector included in the automatic CRC calculation
is CRC0ST x 1024. For 128 kB devices, pages 32–63 access the upper code
bank as selected by the IFBANK bits in the PSBANK SFR.
Read = 00b; Write = Don’t Care.
These bits specify the number of flash sectors to include in an automatic CRC cal-
culation. The starting address of the last flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024. The last page should not
exceed page 63. Setting both CRC0ST and CRC0CNT to 0 will perform a CRC
over the 64kB banked memory space.
6
0
6
1
5
0
5
0
R/W
R/W
Rev. 0.5
4
0
4
0
Function
Function
CRC0CNT[5:0]
3
0
CRC0ST[5:0]
3
0
2
0
2
0
1
0
1
0
R/W
R/W
0
0
0
0