C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 461

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

32.3.2. 8-Bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 32.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the SmaRTClock. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON)
select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in
TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
32.3.3. SmaRTClock/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either SmaRTClock or the external oscillator period to be measured
against the system clock or the system clock divided by 12. SmaRTClock and the external oscillator period
can also be compared against each other.
External Clock / 8
T3MH
SmaRTClock
SYSCLK / 12
0
0
0
0
1
T3XCLK[1:0]
T3XCLK[1:0]
00
01
11
00
01
10
11
X
SYSCLK
Figure 32.8. Timer 3 8-Bit Mode Block Diagram
SYSCLK / 12
SmaRTClock
Reserved
External Clock / 8
SYSCLK
TMR3H Clock
Source
0
1
1
0
M
T
H
3
M
T
3
L
CKCON
M
H
T
2
M
T
2
L
TR3
T
M
1
M
T
0
S
C
A
1
C
S
A
0
Rev. 0.5
TCLK
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
T3ML
0
0
0
0
1
Reload
Reload
T3XCLK[1:0]
00
01
10
11
X
T3XCLK1
T3XCLK0
To ADC
TF3CEN
T3SPLIT
TF3LEN
TF3H
TF3L
TR3
C8051F96x
SYSCLK / 12
SmaRTClock
Reserved
External Clock / 8
SYSCLK
TMR3L Clock
Source
Interrupt
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