STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 97

• Manufacturer Part Number: STM8S105C4B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM8S105xx
10.3.10
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
C
(1)
(2)
(3)
low time.
(4)
the undefined region of the falling edge of SCL.
w(STO:STA)
w(SCLL)
w(SCLH)
su(SDA)
h(SDA)
r(SDA)
r(SCL)
f(SDA)
f(SCL)
h(STA)
su(STA)
su(STO)
b
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
f
Data based on standard I
The maximum hold time of the start condition has only to be met if the interface does not stretch the
MASTER
, must be at least 8 MHz to achieve max fast I
Parameter
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition
setup time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
I
2
C interface characteristics
2
C protocol requirement, not tested in production.
Table 44: I
DocID14771 Rev 9
2
C characteristics
Standard mode I
Min
4.7
4.0
250
0
4.0
4.7
4.0
4.7
(3)
(2)
2
C speed (400kHz).
Max
1000
300
400
(2)
2
C
Fast mode I
Min
1.3
0.6
100
0
0.6
0.6
0.6
1.3
(4)
(2)
Electrical characteristics
Max
900
300
300
400
2
C
(1)
(3)
(2)
Unit
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
pF
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