STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 93

• Manufacturer Part Number: STM8S105C4B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM8S105xx
10.3.9
The reset network shown inthe following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below the V
in the I/O port pin characteristics section. Otherwise the reset is not taken into account
internally.
SPI serial peripheral interface
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
t
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
MASTER
(optional)
External
= 1/f
circuit
reset
Figure 39: Typical NRST pull-up current vs V
MASTER
.
Figure 40: Recommended reset pin protection
0.01 F
DocID14771 Rev 9
NRST
MASTER
VDD
RPU
frequency and V
DD
Filter
@ 4 temperatures
DD
Electrical characteristics
supply voltage conditions.
Internal reset
IL
max. level specified
STM8
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