STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 29
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STM8S105C4B3
Manufacturer Part Number
STM8S105C4B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STM8S105C4B3.pdf
(127 pages)
- Current page: 29 of 127
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STM8S105xx
6
6.1
Memory and register map
Memory map
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
DocID14771 Rev 9
Figure 7: Memory map
0x02 7FFF
0x00 FFFF
0x00 07FF
0x00 43FF
0x00 47FF
0x00 7EFF
0x00 0000
0x00 4000
0x00 4400
0x00 4FFF
0x00 57FF
0x00 5FFF
0x00 67FF
0x00 7FFF
0x00 8000
0x00 807F
0x01 0000
0x00 487F
0x00 7F00
0x00 4800
0x00 4900
0x00 5000
0x00 5800
0x00 6000
0x00 6800
CPU/SWIM/debug/ITC
Flash program memory
1 Kbyte data EEPROM
GPIO and periph. reg.
2 Kbytes boot ROM
(16 to 32 Kbytes)
32 interrupt vectors
512 bytes stack
Option bytes
Reserved
Reserved
(2 Kbytes)
Reserved
Reserved
Reserved
registers
Reserved
RAM
Memory and register map
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