STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 72

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STM8S105C4B3

Manufacturer Part Number
STM8S105C4B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Electrical characteristics
10.3.2.6
10.3.2.7
72/127
Symbol
(4)
(5)
(6)
I
t
(1)
(2)
DD(R)
RESETBL
Configured by the REGAH bit in the CLK_ICKR register.
Configured by the AHALT bit in the FLASH_CR1 register.
Plus 1 LSI clock depending on synchronization.
Data guaranteed by design, not tested in production.
Characterized with all I/Os tied to V
Total current consumption and timing in forced reset state
Current consumption of on-chip peripherals
Subject to general operating conditions for V
HSI internal RC/f
Symbol
Parameter
I
I
I
I
I
I
Supply current in reset
state
Reset pin release to
vector fetch
DD(TIM1)
DD(TIM2)
DD(TIM3)
DD(TIM4)
DD(UART2)
DD(SPI)
Table 30: Total current consumption and timing in forced reset state
(2)
Parameter
TIM1 supply current
TIM2 supply current
TIM3 timer supply current
TIM4 timer supply current
UART2 supply current
SPI supply current
CPU
= f
Table 31: Peripheral current consumption
MASTER
SS
Conditions
V
V
.
DD
DD
DocID14771 Rev 9
= 16 MHz.
= 5 V
= 3.3 V
(2)
(1)
(1)
(2)
(1)
(1)
DD
and T
A
.
Typ.
230
115
90
30
110
45
Typ
500
400
Max
150
STM8S105xx
(1)
Unit
µA
Unit
μA
μs

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