STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 120

• Manufacturer Part Number: STM8S105C4B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Ordering information
120/127
OPT3 watchdog
OPT4 wakeup
AFR4
(check only one option)
AFR5
(check only one option)
AFR6
(check only one option)
AFR7
(check only one option)
WWDG_HALT
(check only one option)
WWDG_HW
(check only one option)
IWDG_HW
(check only one option)
LSI_EN
(check only one option)
HSITRIM
(check only one option)
PRSC
(check only one option)
[ ] 1: Port D0 alternate function = TIM1_BKIN.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port D7 alternate function = TIM1_CH4.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port D4 alternate function = BEEP.
DocID14771 Rev 9
[ ] for 16 MHz to 128 kHz prescaler.
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
[ ] 0: No reset generated on halt if WWDG active.
[ ] 1: Reset generated on halt if WWDG active.
[ ] 0: WWDG activated by software.
[ ] 1: WWDG activated by hardware.
[ ] 0: IWDG activated by software.
[ ] 1: IWDG activated by hardware.
[ ] 0: LSI clock is not available as CPU clock source.
[ ] 1: LSI clock is available as CPU clock source.
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
STM8S105xx