ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 258

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

258
ATA6602/ATA6603
Figure 4-97. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
This is summarized in
Figure 4-98. Possible Status Codes Caused by Arbitration
• Two or more masters are performing identical communication with the same Slave. In this
• Two or more masters are accessing the same Slave with different data or direction bit. In this
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
START
case, neither the Slave nor any of the masters will know about the bus contention.
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
SDA
SCL
Address / General Call
TRANSMITTER
Direction
received
Device 1
MASTER
Own
Yes
Figure
Arbitration lost in SLA
SLA
Write
Read
4-98. Possible status values are given in circles.
TRANSMITTER
Device 2
MASTER
No
Device 3
RECEIVER
SLAVE
68/78
38
B0
Arbitration lost in Data
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
........
Device n
Data
V
CC
R1
R2
4921C–AUTO–01/07
STOP