ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 179

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4921C–AUTO–01/07
• Bit 5 – AS2: Asynchronous Timer/Counter2
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When
AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the
Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2,
OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new
value.
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new
value.
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new
value.
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes
set. When TCCR2A has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated
with a new value.
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes
set. When TCCR2B has been updated from the temporary storage register, this bit is
cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated
with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag
is set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ-
ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B,
TCCR2A and TCCR2B the value in the temporary storage register is read.
ATA6602/ATA6603
179