ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 236

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

236
ATA6602/ATA6603
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
• Bit 5 – TWSTA: TWI START Condition Bit
• Bit 4 – TWSTO: TWI STOP Condition Bit
• Bit 3 – TWWC: TWI Write Collision Flag
• Bit 2 – TWEN: TWI Enable Bit
• Bit 1 – Res: Reserved Bit
• Bit 0 – TWIE: TWI Interrupt Enable
While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be
cleared by software by writing a logic one to it. Note that this flag is not automatically cleared
by hardware when executing the interrupt routine. Also note that clearing this flag starts the
operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status
Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to
one, the ACK pulse is generated on the TWI bus if the following conditions are met:
The device’s own slave address has been received.
A general call has been received, while the TWGCE bit in the TWAR is set.
A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to
one again.
The application writes the TWSTA bit to one when it desires to become a Master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START
condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP
condition is detected, and then generates a new START condition to claim the bus Master
status. TWSTA must be cleared by software when the START condition has been
transmitted.
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared
automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error
condition. This will not generate a STOP condition, but the TWI returns to a well-defined
unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when
TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is writ-
ten to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins,
enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is
switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
This bit is a reserved bit and will always read as zero.
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be
activated for as long as the TWINT Flag is high.
4921C–AUTO–01/07