ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 180

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.15.10
4.15.10.1
180
ATA6602/ATA6603
Timer/Counter Prescaler
General Timer/Counter Control Register – GTCCR
Figure 4-64. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
system I/O clock clk
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
Read/Write
Initial Value
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
T2S
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchro-
nous mode, the bit will remain one until the prescaler has been reset. The bit will not be
cleared by hardware if the TSM bit is set. Refer to the description of the
Timer/Counter Synchronization Mode” on page 130
Synchronization mode.
Bit
/128, clk
T2S
TSM
R/W
PSRASY
TOSC1
7
0
clk I/O
CS20
CS21
CS22
/256, and clk
AS2
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
R
6
–
0
T2S
clk
/1024. Additionally, clk
T2S
R
5
–
0
Clear
R
TIMER/COUNTER2 CLOCK SOURCE
4
–
0
0
T2S
10-BIT T/C PRESCALER
. clk
R
3
–
0
clk
T2S
T2S
T2
for a description of the Timer/Counter
as well as 0 (stop) may be selected.
is by default connected to the main
R
2
–
0
T2S
PSRASY PSRSYNC GTCCR
/8, clk
R/W
1
0
T2S
R/W
/32, clk
4921C–AUTO–01/07
“Bit 7 – TSM:
0
0
T2S
/64,