APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 61

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-50 • T
Symbol t
CCYC
CMH
CML
OCA
OCH
RACH
RACS
RDCH
RDCS
RPCA
RPCH
Note: All –F speed grade devices are 20% slower than the standard numbers.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
Description
RBD, RBLKB
DD
RADDR
DD
RCLKS
= 2.3 V to 2.7 V for Commercial/industrial
DO
RPE
= 2.3 V to 2.7 V for Military/MIL-STD-883
t RACS
t RDCS
t RDCH
t RACH
Old Data Out
New Valid
Address
t OCH
t RPCH
Cycle Start
t CMH
Min.
v5.7
7.5
3.0
3.0
7.5
0.5
1.0
0.5
1.0
9.5
t OCA
t RPCA
t CCYC
Max.
3.0
3.0
New Valid Data Out
t CML
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ProASIC
PLUS
Flash Family FPGAs
Notes
1-55