APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 170

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

3 -6
Previous version
Advanced v0.7
(Advanced v0.6)
ProASIC
PLUS
Flash Family FPGAs
The
The
The
"I/O Features" section
The
section,
Options" section
"PLL Block – Top-Level View and Detailed PLL Block Diagram" section
Figure 1-15
"Sample Implementations"
Minimization" section
Figure
The
The
Figure 1-26
The
The
The
The
The
The
The
The
The
The
The
The
The
Pin AK31 of FG1152 for the APA1000 changed to V
The
The
The
The
The
Table 1-1
Figure 1-14
The
The
The
The
The
The ’Nominal Supply Voltages’ section was updated.
The
The
The
updated.
Changes in current version (v5.7)
"ProASICPLUS Architecture" section
"Array Coordinates" section
"Power-Up Sequencing" section
"PLL Electrical Specifications" section
"Design Environment" section
"Calculating Typical Power Dissipation" section
"DC Electrical Specifications (V
Table 1-22
"DC Specifications (3.3 V PCI Operation)1" section
"Tristate Buffer Delays" section
"Output Buffer Delays" section
"Input Buffer Delays" section
"Global Input Buffer Delays" section
"Predicted Global Routing Delay" section
"Global Routing Skew" section
"Sample Macrocell Library Listing" section
"Pin Description" section
"Recommended Design Practice for VPN/VPP" section
"Features and Benefits" on page i-i
"ProASIC
"Ordering Information" on page i-ii
"Plastic Device Resources" on page i-ii
"ProASICPLUS Architecture" on page 1-2
"Design Environment" section
"Package Thermal Characteristics" section
"Calculating Typical Power Dissipation" section
"Absolute Maximum Ratings*" section
"Programming, Storage, and Operating Limits" section
"Recommended Operating Conditions" section
"DC Electrical Specifications (V
"DC Electrical Specifications (V
"Timing Control and Characteristics" section
1-16,
"Functional Description"
was updated.
was updated.
was updated.
was updated.
Figure
PLUS
was updated.
are new.
Product Profile" on page i-i
1-17,
was updated.
are new.
Figure
section,
was updated. GLMX is new.
1-18,
and
was updated.
DDP
DDP
was updated.
was updated.
DDP
section,
(the figure and table) have been updated.
(the figure and table) have been updated.
was updated.
"Adjustable Clock Delay"
is new.
Table 1-2
Figure
= 2.5 V ±0.2V)" section
= 2.5 V ±0.2V)" section
= 3.3 V ±0.3 V and V
were updated.
was updated.
was updated.
was updated.
is new.
was updated.
was updated.
v5.7
1-19, and
"Lock Signal"
was updated.
was updated.
was updated.
was updated.
was updated.
are new.
was updated.
was updated.
PP
was updated.
was updated.
.
Figure 1-20
was updated.
was updated.
was updated.
section, and
DD
was updated.
was updated.
section, and the
= 2.5 V ±0.2 V)" section
are new.
"Physical Implementation"
was updated.
"PLL Configuration
"Clock Skew
was
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