APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 14

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Array Coordinates
During many place-and-route operations in Actel’s
Designer software tool, it is possible to set constraints
that require array coordinates.
Table 1-2
are measured from the lower left (0,0). They can be used in
region constraints for specific groups of core cells, I/Os, and
RAM blocks. Wild cards are also allowed.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
Table 1-2 •
Figure 1-8 • Core Cell Coordinates for the APA1000
1 -8
Device
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
ProASIC
is provided as a reference. The array coordinates
PLUS
Array Coordinates
Flash Family FPGAs
x
1
1
1
1
1
1
1
(1,169)
(1,167)
(1,165)
(1,164)
Min.
(1,5)
(1,3)
(1,1)
(0,0)
y
1
1
5
5
5
5
5
Logic Tile
128
128
192
224
256
352
96
x
Max.
100
132
164
32
48
68
68
y
Memory
Memory
Blocks
Core
Blocks
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
(1,1) or (1,3)
v5.7
Bottom
y
cells and core cells. In addition, the I/O coordinate system
changes depending on the die/package combination.
Core cell coordinates start at the lower left corner
(represented as (1,1)) or at (1,5) if memory blocks are
present at the bottom. Memory coordinates use the
same system and are indicated in
coordinates for an APA1000 are illustrated in
For more information on how to use constraints, see the
Designer User’s Guide
software tools.
–
–
Memory Rows
(101,101) or (101, 103)
(133,133) or (133, 135)
(165,165) or (165, 167)
(33,33) or (33, 35)
(49,49) or (49, 51)
(69,69) or (69, 71)
(69,69) or (69, 71)
Top
y
or online help for ProASIC
(353,169)
(352,167)
(352,165)
(352,164)
(352,5)
(352,3)
(352,1)
(353,0)
Table
Min.
0,0
0,0
0,0
0,0
0,0
0,0
0,0
1-2. The memory
All
225, 105
257, 137
353, 169
129, 73
193, 73
129, 53
Figure
97, 37
Max.
PLUS
1-8.