APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet

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APA075-BGB

Manufacturer Part Number
APA075-BGB
Description
ProASIC Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
ProASIC
Features and Benefits
High Capacity
Commercial and Industrial
Military
Reprogrammable Flash Technology
Performance
Secure Programming
Low Power
Table 1 • ProASIC
© 2008 Actel Corporation
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
Notes:
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
S e pt em be r 2 0 08
FBGA
CQFP
TQFP
PQFP
PBGA
CCGA/LGA
75,000 to 1 Million System Gates
27 k to 198 kbits of Two-Port SRAM
66 to 712 User I/Os
300, 000 to 1 million System Gates
72 k to 198 kbits of Two Port SRAM
158 to 712 User I/Os
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
2
2
PLUS®
PLUS
Product Profile
Flash Family FPGAs
APA075
100, 144
75,000
3,072
27 k
158
208
144
Yes
Yes
12
24
2
2
4
APA150
144, 256
150,000
6,144
242
100
208
456
36k
Yes
Yes
16
32
2
2
4
®
)
APA300
144, 256
208, 352
300,000
8,192
72 k
290
208
456
Yes
Yes
32
32
High Performance Routing Hierarchy
I/O
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow
ISP Support
SRAMs and FIFOs
2
2
4
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
Schmitt-Trigger Option on Every Input
2.5 V/3.3 V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across the ProASIC
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate Optimization
In-System Programming (ISP) via JTAG Port
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
1
144, 256, 484
APA450
450,000
12,288
108 k
344
208
456
Yes
Yes
48
48
2
2
4
See the Actel website for the latest version of the datasheet.
256, 484, 676
APA600
208, 352
600,000
21,504
126 k
454
208
456
624
Yes
Yes
56
56
2
2
4
1
APA750
676, 896
750,000
32,768
144 k
562
208
456
Yes
Yes
64
64
2
2
4
PLUS
APA1000
Family
1,000,000
896, 1152
208, 352
56,320
198 k
712
208
456
624
Yes
Yes
88
88
2
2
4
v5.7
v5.7
1
®
i

Related parts for APA075-BGB

APA075-BGB Summary of contents

Page 1

... In-System Programming (ISP) via JTAG Port SRAMs and FIFOs • SmartGen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks ® ) • 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) 1 APA075 APA150 APA300 75,000 150,000 300,000 3,072 6,144 8,192 27 k 36k ...

Page 2

... Flash Family FPGAs Ordering Information _ APA1000 F FG Package Type Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 = 75,000 Equivalent System Gates APA150 = 150,000 Equivalent System Gates APA300 = 300,000 Equivalent System Gates APA450 = 450,000 Equivalent System Gates APA600 = ...

Page 3

... Device Resources Commercial/Industrial TQFP TQFP PQFP Device 100-Pin 144-Pin 208-Pin 456-Pin APA075 66 107 158 APA150 66 158 4 APA300 158 APA450 158 4 APA600 158 APA750 158 4 APA1000 158 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2 ...

Page 4

... PLUS ProASIC Flash Family FPGAs Temperature Grade Offerings Package APA075 TQ100 TQ144 PQ208 BG456 FG144 FG256 FG484 FG676 FG896 FG1152 CQ208 CQ352 CG624 Note Commercial I = Industrial M = Military B = MIL-STD-883 Speed Grade and Temperature Matrix Note Commercial I = Industrial M = Military B = MIL-STD-883 iv APA150 ...

Page 5

Table of Contents General Description PLUS ProASIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

...

Page 7

General Description PLUS The ProASIC family of devices, Actel’s second- generation Flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to ...

Page 8

PLUS ProASIC Flash Family FPGAs PLUS ProASIC Architecture PLUS The proprietary ProASIC architecture granularity comparable to gate arrays. PLUS The ProASIC device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., ...

Page 9

(CLK (Reset) Figure 1-3 • Core Logic Tile Live at Power-Up PLUS The Actel Flash-based ProASIC Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing ...

Page 10

PLUS ProASIC Flash Family FPGAs Routing Resources PLUS The routing structure of ProASIC to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global ...

Page 11

Spans 4 Tiles Figure 1-5 • Efficient Long-Line Resources Spans 2 Tiles Spans 1 Tile ...

Page 12

PLUS ProASIC Flash Family FPGAs High Speed Very Long-Line Resouces PAD RING Figure 1-6 • High-Speed, Very Long-Line Resources Clock Resources PLUS The ProASIC family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each ...

Page 13

... Note: This figure shows routing for only one global path. Figure 1-7 • High-Performance Global Network Table 1-1 • Clock Spines Global Clock Networks (Trees) Clock Spines/Tree Total Spines Top or Bottom Spine Height (Tiles) Tiles in Each Top or Bottom Spine Total Tiles PAD RING APA075 APA150 APA300 ...

Page 14

... RAM blocks. Wild cards are also allowed. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O Table 1-2 • Array Coordinates Logic Tile Min. Device x y APA075 1 1 APA150 1 1 APA300 1 5 APA450 1 ...

Page 15

Input/Output Blocks To meet complex system demands, the ProASIC family offers devices with a large number of user I/O pins 712 on the APA1000. available supply voltage configurations (the PLL block uses an independent 2.5 V supply on ...

Page 16

PLUS ProASIC Flash Family FPGAs Power-Up Sequencing PLUS While ProASIC devices are live at power-up, the order of V and V power-up is important during system DD DDP start-up. V should be powered up simultaneously with DD PLUS V on ...

Page 17

Boundary Scan (JTAG) PLUS ProASIC devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The PLUS basic ProASIC boundary-scan logic circuit is composed of the TAP (test access port), ...

Page 18

PLUS ProASIC Flash Family FPGAs The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee ...

Page 19

Timing Control and Characteristics PLUS ProASIC Clock Management System PLUS ProASIC devices provide designers with very flexible clock conditioning capabilities. Each member of the PLUS ProASIC family contains two phase-locked loop (PLL) blocks which perform the following functions: • Clock ...

Page 20

PLUS ProASIC Flash Family FPGAs enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock (in increments of 0.25 ns) relative to the ...

Page 21

Package Pins Physical I/O Buffers GL Std. Pad Cell NPECL PECL Pad Cell PPECL GLMX Std. Pad Cell GL Std. Pad Cell Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL Block Note: When a signal ...

Page 22

PLUS ProASIC Flash Family FPGAs Table 1-8 • Clock-Conditioning Circuitry Delay-Line Settings Delay Line Delay Value (ns) DLYB DLYA Lock Signal An active-high Lock signal (added via the SmartGen PLL development tool) ...

Page 23

Global MUX B OUT 33 MHz External Feedback Global MUX A OUT Figure 1-16 • Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz External Feedback Global MUX A OUT Figure 1-17 • Using ...

Page 24

PLUS ProASIC Flash Family FPGAs Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 1-18 • Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz External Feedback Global MUX A OUT ...

Page 25

On chip Off chip Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Reference clock Figure 1-20 • Using the PLL for Clock Deskewing /1 180˚ ÷n PLL Core 0˚ ÷ SET ...

Page 26

PLUS ProASIC Flash Family FPGAs Logic Tile Timing Characteristics PLUS Timing characteristics for ProASIC three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASIC members. Internal routing delays are device ...

Page 27

PLL Electrical Specifications Parameter Frequency Ranges Reference Frequency f (min.) IN Reference Frequency f (max.) IN OSC Frequency f (min.) VCO OSC Frequency f (max.) VCO Clock Conditioning Circuitry f (min.) OUT Clock Conditioning Circuitry f (max.) OUT Long Term ...

Page 28

... A single memory configuration could include blocks from both the top and bottom memory locations. PLUS Table 1-11 • ProASIC Memory Configurations by Device Device Bottom APA075 0 APA150 0 APA300 16 APA450 24 APA600 28 ...

Page 29

Table 1-12 • Basic Memory Configurations Type Write Access RAM Asynchronous Asynchronous RAM Asynchronous Asynchronous RAM Asynchronous Synchronous Transparent RAM Asynchronous Synchronous Transparent RAM Asynchronous Synchronous Pipelined RAM Asynchronous Synchronous Pipelined RAM Synchronous Asynchronous RAM Synchronous Asynchronous RAM Synchronous Synchronous ...

Page 30

PLUS ProASIC Flash Family FPGAs DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write WCLKS and Sync Read Ports WPE PARODD DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write and WCLKS Async Read Ports WPE PARODD Note: ...

Page 31

DI<0:8> LEVEL<0:7> LGDEP<0:2> FIFO (256x9) WRB WBLKB Sync Write RDB and Sync Read RBLKB Ports PARODD WCLKS DI <0:8> LEVEL <0:7> FIFO LGDEP<0:2> (256x9) WRB WBLKB Async Write RDB and Sync Read RBLKB Ports PARODD Note: Each RAM block contains ...

Page 32

PLUS ProASIC Flash Family FPGAs Word Depth Figure 1-23 • APA1000 Memory Block Architecture Word Width Word 256 Depth 256 256 256 1,024 words x 9 bits, 1 read, 1 write Figure 1-24 • Example Showing Memory Arrays with Different ...

Page 33

Design Environment PLUS The ProASIC family of FPGAs is fully supported by ® both Actel's Libero Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding ...

Page 34

PLUS ProASIC Flash Family FPGAs Related Documents Application Notes Efficient Use of ProASIC Clock Trees http://www.actel.com/documents/A500K_Clocktree_AN.pdf PLUS I/O Features in ProASIC Flash FPGAs http://www.actel.com/documents/APA_LVPECL_AN.pdf PLUS Power-Up Behavior of ProASIC Devices http://www.actel.com/documents/APA_PowerUp_AN.pdf PLUS ProASIC PLL Dynamic Reconfiguration Using JTAG http://www.actel.com/documents/APA_PLLdynamic_AN.pdf PLUS ...

Page 35

... Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Ceramic Column Grid Array (CCGA/LGA) Notes: 1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 3. Depopulated Array 4. Full array the maximum allowable temperature on the active surface of the IC and is 110° ...

Page 36

... Total Power Consumption—P total total dc ac where for the APA075 for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 P includes the static components ...

Page 37

Logic-Tile Contribution—P logic P , the logic-tile component of AC power dissipation, is given by logic logic where: 1.4 μW/MHz is the average power consumption of a logic tile per MHz of its ...

Page 38

PLUS ProASIC Flash Family FPGAs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. ...

Page 39

Operating Conditions Standard and –F parts are the same unless otherwise noted. All –F parts are only available as commercial. Table 1-16 • Absolute Maximum Ratings* Parameter Supply Voltage Core ( Supply Voltage I/O Ring (V ) DDP ...

Page 40

PLUS ProASIC Flash Family FPGAs Table 1-18 • Military Temperature Grade Product Performance Retention Minimum Time at T Minimum Time 110°C or below 125°C or below 100% 90% 10% 75% 25% 90% 50% 50% 90% 75% 100% ...

Page 41

Table 1-19 • Recommended Maximum Operating Conditions Programming and PLL Supplies Parameter Condition V During Programming PP Normal Operation V During Programming PN Normal Operation I During Programming PP I During Programming PN AVDD AGND Notes: 1. Please refer to ...

Page 42

PLUS ProASIC Flash Family FPGAs Table 1-21 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH High Drive (OB25LPH) Low Drive (OB25LPL) V Output Low Voltage OL High Drive (OB25LPH) Low Drive (OB25LPL Input High ...

Page 43

Table 1-21 • DC Electrical Specifications (V Symbol Parameter I Output Short Circuit Current High OSH High Drive (OB25LPH) Low Drive (OB25LPL) I Output Short Circuit Current Low OSL High Drive (OB25LPH) Low Drive (OB25LPL) C I/O Pad Capacitance I/O ...

Page 44

PLUS ProASIC Flash Family FPGAs Table 1-22 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive (OB33P) 3.3 V I/O, Low Drive (OB33L) V Output Low Voltage OL 3.3 V I/O, High ...

Page 45

Table 1-22 • DC Electrical Specifications (V Symbol Parameter I Tristate Output Leakage OZ Current I Output Short Circuit Current OSH High 3.3 V High Drive (OB33P) 3.3 V Low Drive (OB33L) I Output Short Circuit Current OSL Low 3.3 ...

Page 46

PLUS ProASIC Flash Family FPGAs Table 1-23 • DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Core DD V Supply Voltage for I/O Ring DDP V Input High Voltage IH V Input Low Voltage IL 4 ...

Page 47

Table 1-24 • AC Specifications (3.3 V PCI Revision 2.2 Operation) Symbol Parameter Condition I Switching Current High 0 < V OH(AC) 0.3V 0.7V (Test Point) V OUT I Switching Current Low V OL(AC) DDP 0.6V 0.18V (Test Point) V ...

Page 48

PLUS ProASIC Flash Family FPGAs Tristate Buffer Delays A 50% 50 PAD 50 DLH DHL Figure 1-26 • Tristate Buffer Delays Table 1-25 • Worst-Case Commercial Conditions 2.3 ...

Page 49

Table 1-27 • Worst-Case Military Conditions load, T DDP DD Macro Type Description OTB33PH 3.3 V, PCI Output Current, High Slew Rate OTB33PN 3.3 V, High Output Current, Nominal Slew ...

Page 50

PLUS ProASIC Flash Family FPGAs Output Buffer Delays A OBx Figure 1-27 • Output Buffer Delays Table 1-29 • Worst-Case Commercial Conditions load, T DDP DD Macro Type OB33PH 3.3 ...

Page 51

Table 1-31 • Worst-Case Military Conditions V = 3.0V 2.3V load, T DDP DD Macro Type Description OB33PH 3.3V, PCI Output Current, High Slew Rate OB33PN 3.3V, High Output Current, Nominal Slew Rate OB33PL 3.3V, High ...

Page 52

PLUS ProASIC Flash Family FPGAs Input Buffer Delays PAD Figure 1-28 • Input Buffer Delays Table 1-33 • Worst-Case Commercial Conditions DDP DD Macro Type IB33 3.3 V, CMOS Input Levels ...

Page 53

Table 1-35 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type Description IB33 3.3V, CMOS Input Levels IB33S 3.3V, CMOS Input Levels Notes Input Pad-to-Y High INYH Input ...

Page 54

PLUS ProASIC Flash Family FPGAs Global Input Buffer Delays Table 1-37 • Worst-Case Commercial Conditions DDP DD Macro Type GL33 3.3 V, CMOS Input Levels GL33S 3.3 V, CMOS Input Levels ...

Page 55

Table 1-39 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type GL33 3.3V, CMOS Input Levels GL33S 3.3V, CMOS Input Levels PECL PPECL Input Levels Notes Input Pad-to-Y High INYH 2. ...

Page 56

PLUS ProASIC Flash Family FPGAs Predicted Global Routing Delay Table 1-41 • Worst-Case Commercial Conditions DDP DD Parameter Description 3 t Input Low to High RCKH 3 t Input High to ...

Page 57

Module Delays Figure 1-29 • Module Delays Sample Macrocell Library Listing Table 1-45 • Worst-Case Military Conditions 70º Cell Name NAND2 2-Input NAND AND2 2-Input AND ...

Page 58

PLUS ProASIC Flash Family FPGAs Table 1-46 • Recommended Operating Conditions Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* • Schmitt Trigger Mode (10% to 90%) • Non-Schmitt Trigger Mode (10% to 90%) Maximum LVPECL Frequency* ...

Page 59

Table 1-48 • JTAG Switching Characteristics Description Output delay from TCK falling to TDI, TMS TDO Setup time before TCK rising TDO Hold time after TCK rising TCK period RCK period Notes: 1. For DC electrical specifications of the JTAG ...

Page 60

PLUS ProASIC Flash Family FPGAs Embedded Memory Specifications PLUS This section discusses ProASIC SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks Table 1-12 on ...

Page 61

Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RBD, RBLKB RADDR Note: The plot shows the normal operation status. Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-50 • 0°C to ...

Page 62

PLUS ProASIC Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RDB, RBLKB New Valid RADDR Address DO RPE t RACS t RACH t RDCH t RDCS Note: The plot shows the normal operation status. Figure 1-32 ...

Page 63

Asynchronous SRAM Write WADDR WRB, WBLKB Note: The plot shows the normal operation status. Figure 1-33 • Asynchronous SRAM Write Table 1-52 • 0°C to 110° 2 2.7 V for Commercial/industrial ...

Page 64

PLUS ProASIC Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE Note: The plot shows the normal operation status. Figure 1-34 • Asynchronous SRAM Read, Address Controlled, RDB=0 Table 1-53 • 0°C to 110°C; V ...

Page 65

Asynchronous SRAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE Note: The plot shows the normal operation status. Figure 1-35 • Asynchronous SRAM Read, RDB Controlled Table 1-54 • 0°C to 110° 2 2.7 V for ...

Page 66

PLUS ProASIC Flash Family FPGAs Synchronous SRAM Write WCLKS WRB, WBLKB WADDR, DI WPE t WRCH , t WBCH t WRCS , t WBCS t DCS , t WDCS t WPCH t DCH , t WACH Note: The plot shows ...

Page 67

Synchronous Write and Read to the Same Location RCLKS DO Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA * New data is read if WCLKS ↑ occurs before setup time. The data stored is read if ...

Page 68

PLUS ProASIC Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location RCLKS Last Cycle Data {WRB + WBLKB WRCKS t BRCLKH t OCH t OCA t DWRRCLKS Note: The plot shows the ...

Page 69

Asynchronous Write and Read to the Same Location RB, RADDR {WRB+WBLKB} t ORDA t ORDH t RAWRS Note: The plot shows the normal operation status. Figure 1-39 • Asynchronous Write and Read to the Same Location Table ...

Page 70

PLUS ProASIC Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO WCLKS t ORDA t ORDH t RAWCLKS Note: The plot shows the normal operation status. Figure 1-40 • Synchronous Write and Asynchronous Read ...

Page 71

Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem ...

Page 72

PLUS ProASIC Flash Family FPGAs FULL RB Write Write inhibited cycle WB Note: All –F speed grade devices are 20% slower than the standard numbers. Figure 1-41 • Write Timing Diagram EMPTY WB Read Read inhibited cycle RB Note: All ...

Page 73

Asynchronous FIFO Read RB = (RDB+RBLKB) RDATA EMPTY EQTH, GETH t RDWRS Note: The plot shows the normal operation status. Figure 1-43 • Asynchronous FIFO Read Table 1-61 • 0°C to 110° 2 2.7 ...

Page 74

PLUS ProASIC Flash Family FPGAs Asynchronous FIFO Write WB = (WRB+WBLKB) WDATA EQTH, GETH Note: The plot shows the normal operation status. Figure 1-44 • Asynchronous FIFO Write Table 1-62 • 0°C to 110° 2.3 V ...

Page 75

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-63 • ...

Page 76

PLUS ProASIC Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH t RDCS Note: The plot shows the normal operation status. Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs ...

Page 77

Synchronous FIFO Write WCLKS WRB, WBLKB WPE FULL EMPTY EQTH, GETH t WRCH , t WBCH t WRCS , t WBCS Note: The plot shows the normal operation status. Figure 1-47 • Synchronous FIFO Write Table 1-65 • ...

Page 78

PLUS ProASIC Flash Family FPGAs FIFO Reset RESETB 1 WRB/RBD 1 WCLKS, RCLKS FULL EMPTY EQTH, GETH t ERSA , t FRSA t THRSA Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) ...

Page 79

Pin Description User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL specifications. Unused I/O pins are configured as inputs with pull-up resistors. ...

Page 80

... Capacitor Requirements . v5.7 and bypass capacitance to counteract and V pins may incur a voltage PP PN devices. Bypass capacitors are required for pads. Use a 0.01 µF to 0.1 µF ceramic PN 1-49). PLUS Devices – APA075, APA150 Programming Header or Supplies _ + pins and the and PP PP ...

Page 81

Package Pin Assignments 100-Pin TQFP 100 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 100-Pin TQFP v5.7 PLUS Flash Family FPGAs 2-1 ...

Page 82

... I/O I/O 58 I/O I/O 59 I/O I/O 60 I/O / GL3 I/O / GL3 61 PPECL2 / Input PPECL2 / Input 62 AVDD AVDD 63 NPECL2 NPECL2 64 AGND AGND 65 I/O / GL4 I/O / GL4 66 I/O / GLMX2 I/O / GLMX2 67 GND GND I/O I/O 70 I/O I/O v5.7 100-Pin TQFP Pin APA075 APA150 Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 GND GND DDP DDP 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O I/O ...

Page 83

TQFP 144 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 144-Pin TQFP v5.7 PLUS Flash Family FPGAs 2-3 ...

Page 84

... GND DDP 100 65 I/O 101 66 I/O 102 67 I/O 103 68 I/O 104 69 TCK 105 70 TDI 106 71 TMS 107 72 NC 108 v5.7 144-Pin TQFP Pin APA075 APA075 Function Number Function V 109 I 110 I/O PN TDO 111 I/O TRST 112 I/O RCK 113 I/O I/O 114 I/O I/O 115 I/O I/O 116 I/O V 117 V DDP DDP GND ...

Page 85

PQFP 208 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 208-Pin PQFP v5.7 PLUS Flash Family FPGAs 2-5 ...

Page 86

... PLUS ProASIC Flash Family FPGAs Pin APA075 APA150 Number Function Function 1 GND GND 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I GND GND 18 I/O 19 I/O 20 I DDP 23 I/O / GLMX1 I/O / GLMX1 24 I/O / GL2 I/O / GL2 25 AGND AGND 26 NPECL1 NPECL1 27 AVDD AVDD 28 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input ...

Page 87

... Pin APA075 APA150 Number Function Function I/O I/O 38 I/O I/O 39 I/O I DDP DDP 41 GND GND 42 I/O I/O 43 I/O I/O 44 I/O I/O 45 I/O I/O 46 I/O I/O 47 I/O I/O 48 I/O I/O 49 I/O I/O 50 I/O I/O 51 I/O I/O 52 GND GND DDP DDP 54 I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 I/O I/O 59 I/O I/O 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 GND GND 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 208-Pin PQFP APA300 APA450 APA600 Function ...

Page 88

... PLUS ProASIC Flash Family FPGAs Pin APA075 APA150 Number Function Function DDP 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 GND GND 82 I/O 83 I/O 84 I/O 85 I/O 86 I DDP 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 GND GND 98 I/O 99 I/O 100 I/O 101 TCK TCK 102 TDI ...

Page 89

... Pin APA075 APA150 Number Function Function 106 107 108 TDO TDO 109 TRST TRST 110 RCK RCK 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O 116 I/O I/O 117 I/O I/O 118 I/O I/O 119 I/O I/O 120 I/O I/O 121 I/O I/O 122 GND GND 123 V V DDP DDP 124 I/O I/O 125 ...

Page 90

... PLUS ProASIC Flash Family FPGAs Pin APA075 APA150 Number Function Function 141 GND GND 142 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 GND GND 157 V V DDP 158 I/O 159 I/O 160 I/O 161 I/O 162 GND ...

Page 91

... Pin APA075 APA150 Number Function Function 176 I/O I/O 177 I/O I/O 178 GND GND 179 I/O I/O 180 I/O I/O 181 I/O I/O 182 I/O I/O 183 I/O I/O 184 I/O I/O 185 I/O I/O 186 V V DDP DDP 187 188 I/O I/O 189 I/O I/O 190 I/O I/O 191 I/O I/O 192 I/O I/O 193 I/O I/O 194 I/O I/O 195 GND GND 196 I/O I/O 197 I/O I/O 198 I/O I/O 199 I/O I/O 200 I/O I/O 201 ...

Page 92

PLUS ProASIC Flash Family FPGAs 208-Pin CQFP No Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource ...

Page 93

CQFP Pin APA300 APA600 Number Function Function 1 GND GND 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...

Page 94

PLUS ProASIC Flash Family FPGAs 208-Pin CQFP Pin APA300 APA600 Number Function Function DDP DDP 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O ...

Page 95

CQFP Pin APA300 APA600 Number Function Function 141 GND GND 142 143 I/O I/O 144 I/O I/O 145 I/O I/O 146 I/O I/O 147 I/O I/O 148 I/O I/O 149 I/O I/O 150 I/O I/O ...

Page 96

PLUS ProASIC Flash Family FPGAs 352-Pin CQFP Pin Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource ...

Page 97

CQFP APA300 APA600 Pin Number Function Function 1 I/O I/O 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I GND GND DDP DDP 10 ...

Page 98

PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA300 APA600 Pin Number Function Function 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I GND GND DDP ...

Page 99

CQFP APA300 APA600 Pin Number Function Function 149 I/O I/O 150 I/O I/O 151 I/O I/O 152 I/O I/O 153 I/O I/O 154 I/O I/O 155 V V DDP DDP 156 GND GND 157 158 ...

Page 100

PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA300 APA600 Pin Number Function Function 223 NPECL2 NPECL2 224 AVDD AVDD 225 AGND AGND 226 I/O / GL4 I/O / GL4 227 I/O / GLMX2 I/O / GLMX2 228 I/O I/O 229 ...

Page 101

CQFP APA300 APA600 Pin Number Function Function 297 V V DDP DDP 298 I/O I/O 299 I/O I/O 300 I/O I/O 301 I/O I/O 302 I/O I/O 303 I/O I/O 304 I/O I/O 305 I/O I/O 306 V V ...

Page 102

PLUS ProASIC Flash Family FPGAs 456-Pin PBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx ...

Page 103

Pin APA150 APA300 Number Function Function A1 V DDP A2 V DDP I/O A9 I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 I/O A15 I/O A16 I/O ...

Page 104

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function B9 I/O B10 I/O B11 I/O B12 I/O B13 I/O B14 I/O B15 I/O B16 I/O B17 I/O B18 I/O B19 I/O B20 NC B21 NC B22 NC B23 NC B24 ...

Page 105

Pin APA150 APA300 Number Function Function C17 I/O C18 I/O C19 I/O C20 I/O C21 NC C22 NC C23 NC C24 V DDP C25 NC C26 DDP ...

Page 106

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function D25 NC D26 I/O E10 I/O E11 I/O E12 ...

Page 107

Pin APA150 APA300 Number Function Function F23 NC F24 NC F25 NC F26 NC G1 I G22 V DD G23 NC G24 NC G25 NC G26 I/O H1 I/O H2 I/O ...

Page 108

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function K1 I/O K2 I/O K3 I/O K4 I/O K5 I/O K22 I/O K23 I/O K24 I/O K25 I/O K26 I/O L1 I/O L2 I/O L3 I/O L4 I/O L5 I/O L11 ...

Page 109

Pin APA150 APA300 Number Function Function M14 GND M15 GND M16 GND M22 I/O / GL4 I/O / GL4 M23 I/O M24 I/O M25 I/O M26 I/O N1 I/O N2 I/O / GLMX1 I/O / GLMX1 N3 AGND N4 PPECL1 ...

Page 110

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function P16 GND P22 I/O P23 I/O P24 I/O P25 I/O P26 PPECL2 / Input R1 I/O R2 I/O R3 I/O R4 I/O R5 I/O R11 GND R12 GND R13 GND R14 ...

Page 111

Pin APA150 APA300 Number Function Function T23 I/O T24 I/O T25 I/O T26 I/O U1 I/O U2 I/O U3 I/O U4 I/O U5 I/O U22 I/O U23 I/O U24 I/O U25 I/O U26 I/O V1 I/O V2 I/O V3 I/O ...

Page 112

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function Y1 I/O Y2 I Y22 V DD Y23 NC Y24 NC Y25 NC Y26 NC AA1 I/O AA2 NC AA3 NC AA4 NC AA5 ...

Page 113

Pin APA150 APA300 Number Function Function AB15 I/O AB16 I/O AB17 I/O AB18 I/O AB19 I/O AB20 V DD AB21 V DD AB22 V DD AB23 NC AB24 NC AB25 NC AB26 NC AC1 NC AC2 NC AC3 NC AC4 ...

Page 114

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function AC23 V DDP AC24 RCK AC25 NC AC26 NC AD1 NC AD2 NC AD3 V DDP AD4 NC AD5 NC AD6 NC AD7 I/O AD8 I/O AD9 I/O AD10 I/O AD11 ...

Page 115

Pin APA150 APA300 Number Function Function AE5 NC AE6 NC AE7 NC AE8 I/O AE9 I/O AE10 I/O AE11 I/O AE12 I/O AE13 I/O AE14 I/O AE15 I/O AE16 I/O AE17 I/O AE18 I/O AE19 I/O AE20 NC AE21 NC ...

Page 116

PLUS ProASIC Flash Family FPGAs Pin APA150 Number Function AF13 I/O AF14 I/O AF15 I/O AF16 I/O AF17 I/O AF18 NC AF19 NC AF20 NC AF21 NC AF22 NC AF23 TDI AF24 NC AF25 V DDP AF26 V DDP 2 ...

Page 117

FBGA 12 11 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.7 PLUS ProASIC Flash Family FPGAs ...

Page 118

... B11 GND GND B12 I/O I/O C1 I/O I/O C2 I/O / GL1 I/O / GL1 I/O / GL1 C3 I/O I I/O I/O C6 I/O I/O C7 I/O I/O C8 I/O I/O C9 I/O I/O C10 I/O I/O C11 I/O I/O C12 I/O I/O D1 I/O I APA450 Pin APA075 Function Number Function I/O I/O D2 I/O I/O D3 I/O I/O D4 I/O I/O D5 I/O I/O D6 GND GND D7 I/O I I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O I/O E1 I/O I/O E2 GND GND E3 I/O I/O ...

Page 119

... L11 I/O I/O L12 I/O I/O M2 I/O I DDP DDP M4 I/O I/O M5 I/O I/O M6 I/O I TCK TCK M9 I/O I/O M10 TDO TDO M11 I/O I/O M12 I/O I/O v5.7 PLUS ProASIC Flash Family FPGAs 144-FBGA Pin APA075 APA150 APA300 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O ...

Page 120

PLUS ProASIC Flash Family FPGAs 256-Pin FBGA 15 16 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...

Page 121

FBGA Pin APA150 APA300 APA450 Number Function Function Function A1 GND GND A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O ...

Page 122

PLUS ProASIC Flash Family FPGAs 256-Pin FBGA Pin APA150 APA300 Number Function Function Function DDP DDP E8 I/O I/O E9 I/O I/O E10 V V DDP DDP E11 V V DDP DDP E12 I/O I/O E13 I/O ...

Page 123

FBGA Pin APA150 APA300 APA450 Number Function Function Function J12 I/O I/O J13 PPECL2 / PPECL2 / PPECL2 / Input Input J14 I/O I/O J15 AVDD AVDD J16 I/O / GL3 I/O / GL3 I/O / GL3 K1 I/O ...

Page 124

PLUS ProASIC Flash Family FPGAs 256-Pin FBGA Pin APA150 APA300 Number Function Function Function P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 I/O I/O P8 I/O I/O P9 I/O ...

Page 125

FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.7 PLUS ...

Page 126

PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function A1 GND GND A2 GND GND DDP DDP A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 ...

Page 127

FBGA Pin APA450 APA600 Number Function Function E21 I/O I/O E22 I/O I/O F1 I/O I/O F2 I/O I/O F3 I/O I/O F4 I/O I/O F5 I/O I/O F6 I/O I/O F7 I/O I/O F8 I/O I/O F9 I/O ...

Page 128

PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function K19 I/O I/O K20 I/O I/O K21 I/O I/O K22 I/O I I/O L2 I/O I/O L3 I/O I/O L4 I/O / GL1 I/O / ...

Page 129

FBGA Pin APA450 APA600 Number Function Function R15 I/O I/O R16 I/O I/O R17 I/O I/O R18 I/O I/O R19 I/O I/O R20 R21 I/O I/O R22 I/O I/O T1 I/O I/O T2 I/O I/O ...

Page 130

PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function Y13 I/O I/O Y14 Y15 Y16 I/O I/O Y17 I/O I/O Y18 GND GND Y19 I/O I/O Y20 I/O ...

Page 131

FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.7 PLUS ProASIC Flash Family FPGAs ...

Page 132

PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function A1 GND GND A2 GND GND A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O ...

Page 133

FBGA Pin APA600 APA750 Number Function Function E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 I/O I/O E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O ...

Page 134

PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function J3 I/O I/O J4 I/O I/O J5 I/O I/O J6 I/O I DDP DDP J10 V ...

Page 135

FBGA Pin APA600 APA750 Number Function Function N4 I/O I/O N5 NPECL1 NPECL1 N6 I/O I DDP DDP N10 GND GND N11 GND GND N12 GND GND N13 ...

Page 136

PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function U3 I/O I/O U4 I/O I/O U5 I/O I/O U6 I/O I DDP DDP U10 GND ...

Page 137

FBGA Pin APA600 APA750 Number Function Function AA4 I/O I/O AA5 I/O I/O AA6 GND GND AA7 I/O I/O AA8 I/O I/O AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O ...

Page 138

PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function AE5 I/O I/O AE6 I/O I/O AE7 I/O I/O AE8 I/O I/O AE9 I/O I/O AE10 I/O I/O AE11 I/O I/O AE12 I/O I/O AE13 I/O I/O ...

Page 139

FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...

Page 140

PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function A2 GND GND A3 GND GND A4 I/O I/O A5 GND GND A6 I/O I/O A7 GND GND A8 I/O I/O A9 I/O I/O A10 I/O I/O ...

Page 141

FBGA Pin APA750 APA1000 Number Function Function D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O D19 I/O I/O D20 I/O I/O D21 I/O I/O D22 I/O I/O D23 I/O I/O D24 I/O I/O D25 I/O ...

Page 142

PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function G27 I/O I/O G28 I/O I/O G29 I/O I/O G30 GND GND H1 I/O I/O H2 I/O I/O H3 I/O I/O H4 I/O I/O H5 I/O I/O ...

Page 143

FBGA Pin APA750 APA1000 Number Function Function L9 NC I/O L10 NC I/O L11 L12 L13 L14 L15 L16 ...

Page 144

PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function P21 V V DDP DDP P22 I/O I/O P23 I/O I/O P24 I/O I/O P25 I/O I/O P26 I/O I/O P27 I/O I/O P28 I/O I/O P29 ...

Page 145

FBGA Pin APA750 APA1000 Number Function Function V3 I/O I/O V4 I/O I/O V5 I/O I/O V6 I/O I/O V7 I/O I/O V8 I/O I I/O V10 V V DDP DDP V11 V12 ...

Page 146

PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AA15 V V DDP DDP AA16 V V DDP DDP AA17 V V DDP DDP AA18 V V DDP DDP AA19 V V DDP DDP AA20 NC ...

Page 147

FBGA Pin APA750 APA1000 Number Function Function AD27 I/O I/O AD28 I/O I/O AD29 I/O I/O AD30 GND GND AE1 I/O I/O AE2 AE3 I/O I/O AE4 I/O I/O AE5 I/O I/O AE6 GND GND ...

Page 148

PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AH9 I/O I/O AH10 I/O I/O AH11 I/O I/O AH12 I/O I/O AH13 I/O I/O AH14 I/O I/O AH15 I/O I/O AH16 I/O I/O AH17 I/O I/O ...

Page 149

FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...

Page 150

PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Pin Number Function Number GND A4 GND A5 GND A6 I/O B10 A7 V B11 B12 B13 DD A10 V B14 DD ...

Page 151

FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number E15 I/O F18 E16 I/O F19 E17 I/O F20 E18 I/O F21 E19 I/O F22 E20 I/O F23 E21 I/O F24 E22 I/O F25 E23 I/O F26 E24 I/O F27 ...

Page 152

PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Pin Number Function Number J27 I/O K30 J28 V K31 DDP J29 I/O K32 J30 I/O K33 J31 I/O K34 J32 GND J33 I/O J34 ...

Page 153

FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number I/O R10 P8 I/O R11 P9 I/O R12 P10 I/O R13 P11 I/O R14 P12 V R15 DDP P13 V R16 DD P14 ...

Page 154

PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Pin Number Function Number V16 GND W18 V17 GND W19 V18 GND W20 V19 GND W21 V20 GND W22 V21 GND W23 V22 V W24 DD V23 V W25 DDP V24 ...

Page 155

FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AB27 I/O AC30 AB28 I/O AC31 AB29 I/O AC32 AB30 I/O AC33 AB31 I/O AC34 AB32 I/O AD1 AB33 I/O AD2 AB34 I/O AD3 AC1 GND AD4 AC2 GND AD5 ...

Page 156

PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Pin Number Function Number AG5 I/O AH8 AG6 I/O AH9 AG7 I/O AH10 AG8 GND AH11 AG9 I/O AH12 AG10 I/O AH13 AG11 I/O AH14 AG12 I/O AH15 AG13 I/O AH16 ...

Page 157

FBGA 1152-Pin FBGA Pin APA1000 Pin Number Function Number AL17 I/O AM20 AL18 I/O AM21 AL19 I/O AM22 AL20 I/O AM23 AL21 I/O AM24 AL22 I/O AM25 AL23 I/O AM26 AL24 I/O AM27 AL25 I/O AM28 AL26 I/O AM29 ...

Page 158

PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA ...

Page 159

CCGA/LGA Pin APA600 APA1000 Number Function Function A2 I/O I/O A3 I/O I/O A4 I/O I/O A5 I/O I/O A6 I/O I/O A7 I/O I/O A8 I/O I/O A9 I/O I/O A10 I/O I/O A11 I/O I/O A12 I/O ...

Page 160

PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function E7 I/O I/O E8 I/O I/O E9 I/O I/O E10 I/O I/O E11 I/O I/O E12 I/O I/O E13 I/O I/O E14 I/O I/O E15 I/O I/O ...

Page 161

CCGA/LGA Pin APA600 APA1000 Number Function Function J12 GND GND J13 GND GND J14 GND GND J15 GND GND J16 GND GND J17 GND GND J18 V V DDP DDP J19 I/O I/O J20 GND GND J21 I/O I/O ...

Page 162

PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function N16 N17 GND GND N18 V V DDP DDP N19 I/O I/O N20 I/O / GL3 I/O / GL3 N21 PPECL2 / PPECL2 ...

Page 163

CCGA/LGA Pin APA600 APA1000 Number Function Function U20 GND GND U21 I/O I/O U22 I/O I/O U23 I/O I/O U24 I/O I/O U25 I/O I/O V1 I/O I/O V2 I/O I/O V3 GND GND V4 I/O I/O V5 I/O ...

Page 164

PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function AA25 I/O I/O AB1 I/O I/O AB2 I/O I/O AB3 I/O I/O AB4 I/O I/O AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O ...

Page 165

Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (v5.7) v5.6 V and V data (August 2008) v5.5 V ...

Page 166

PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.7) v4.1 In the "624-Pin CCGA/LGA" Pin Number M6 M7 M19 M20 N5 N6 N20 N21 MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B ...

Page 167

... Minimum in the IL In the "Output Buffer Delays" In the "Sample Macrocell Library Listing" and the –F maximum changed to 0.8. PLUS and ProASIC Military/Aerospace datasheets were combined. This was updated. was updated. "PLL Electrical Specifications" table was updated. is new. is new. was updated. was updated. ...

Page 168

PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.7) v2.0 The Table 1 was updated. The "Ordering Information" section The "Plastic Device Resources" section The "ProASICPLUS Architecture" section Table 1-2 was updated. Table 1-8 is new. Figure ...

Page 169

Previous version Changes in current version (v5.7) v2.0 (continued) The following pins have been changed in the Pin Number C2 D12 E11 F1 F3 The following pins have been changed in the Pin Number H13 H14 The ...

Page 170

PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.7) Advanced v0.7 The "ProASICPLUS Architecture" section The "Array Coordinates" section The "Power-Up Sequencing" section "I/O Features" section The "Timing Control and Characteristics" section section, "Functional Description" Options" section ...

Page 171

Previous version Changes in current version (v5.7) Advanced v0.6 The "Synchronous Write and Read to the Same Location" section (continued) The "Asynchronous Write and Synchronous Read to the Same Location" section The "Asynchronous FIFO Read" section The "Pin Description" section ...

Page 172

... Flash Family FPGAs Data Sheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definition of these categories are as follows: ...

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...

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Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court,Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 USA ...

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