APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 27

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

PLL Electrical Specifications
Parameter
Frequency Ranges
Reference Frequency f
Reference Frequency f
OSC Frequency f
OSC Frequency f
Clock Conditioning Circuitry f
Clock Conditioning Circuitry f
Long Term Jitter Peak-to-Peak Max.*
25°C (or higher)
0°C
–40°C
–55°C
Acquisition Time from Cold Start
Acquisition Time (max.)
Acquisition Time (max.)
Power Consumption
Analog Supply Power (max.*)
Digital Supply Current (max.)
Duty Cycle
Input Jitter Tolerance
Note: *High clock frequencies (>60 MHz) under typical setup conditions
Temperature
VCO
VCO
(min.)
(max.)
IN
IN
(min.)
(max.)
OUT
OUT
(min.)
(max.)
f
VCO
±1.5%
±2.5%
±2.5%
±1%
5% input period (max. 5 ns)
<10
Frequency MHz
6.9 mW per PLL
50% ±0.5%
10<f
7
180 MHz
180 MHz
180 MHz
1.5 MHz
24 MHz
μ
Value
6 MHz
±2.5%
±3.5%
±3.5%
30
80
W/MHz
±2%
VCO
μ
μ
s
s
v5.7
<60
f
VCO
±1%
±1%
±1%
±1%
>60
Clock conditioning circuitry (min.) lowest input frequency
Clock conditioning circuitry (max.) highest input frequency
Lowest output frequency voltage controlled oscillator
Highest output frequency voltage controlled oscillator
Lowest output frequency clock conditioning circuitry
Highest output frequency clock conditioning circuitry
For example:
Jitter in picoseconds at 100 MHz
= 0.01 * (1/100E6) = 100 ps
f
f
Maximum jitter allowable on an input clock to
acquire and maintain lock.
Jitter(ps) = Jitter(%)*period
VCO
VCO
≤ 40 MHz
> 40 MHz
ProASIC
Notes
PLUS
Flash Family FPGAs
1-21