APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 24
APA075-BGB
Manufacturer Part Number
APA075-BGB
Description
ProASIC Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.APA075-BGB.pdf
(174 pages)
- Current page: 24 of 174
- Download datasheet (5Mb)
Figure 1-18 • Using the PLL to Delay the Input Clock
Figure 1-19 • Using the PLL to Advance the Input Clock
1 -1 8
ProASIC
PLUS
Global MUX B OUT
Global MUX A OUT
Flash Family FPGAs
External Feedback
Global MUX B OUT
Global MUX A OUT
External Feedback
133 MHz
133 MHz
÷1
÷m
÷n
÷1
÷1
÷m
÷n
÷1
D
D
PLL Core
PLL Core
v5.7
D
D
180
0
180
0
˚
˚
˚
˚
÷u
÷v
÷1
÷u
÷v
÷1
133 MHz
133 MHz
D
D
D
D
GLB
GLA
GLB
GLA
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