am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 81

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

EEPROM Interface
The Am79C972 controller contains a built-in capability
for reading and writing to an external serial 93C46
EEPROM. This built-in capability consists of an inter-
face for direct connection to a 93C46 compatible
EEPROM, an automatic EEPROM read feature, and a
user-programmable register that allows direct access
to the interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the RST pin, the
Am79C972 controller will read the contents of the
EEPROM that is attached to the interface. Because of
this automatic-read capability of the Am79C972 con-
troller, an EEPROM can be used to program many of
the features of the Am79C972 controller at power-up,
allowing system-dependent configuration information
to be stored in the hardware, instead of inside the
device driver.
If an EEPROM exists on the interface, the Am79C972
controller will read the EEPROM contents at the end of
the H_RESET operation. The EEPROM contents will
be serially shifted into a temporary register and then
sent to various register locations on board the
Am79C972 controller. Access to the Am79C972 con-
figuration space, the Expansion ROM or any I/O
resource is not possible during the EEPROM read op-
eration. The Am79C972 controller will terminate any
access attempt with the assertion of DEVSEL and
STOP while TRDY is not asserted, signaling to the ini-
tiator to disconnect and retry the access at a later time.
A checksum verification is performed on the data that
is read from the EEPROM. If the checksum verification
passes, PVALID (BCR19, bit 15) will be set to 1. If the
checksum verification of the EEPROM data fails,
PVALID will be cleared to 0, and the Am79C972 con-
troller will force all EEPROM-programmable BCR reg-
isters back to their H_RESET default values. However,
the content of the Address PROM locations (offsets
0h - Fh from the I/O or memory mapped I/O base ad-
dress) will not be cleared. The 8-bit checksum for the
entire 68 bytes of the EEPROM should be FFh.
If no EEPROM is present at the time of the automatic
read operation, the Am79C972 controller will recognize
this condition and will abort the automatic read opera-
tion and clear both the PREAD and PVALID bits in
BCR19. All EEPROM-programmable BCR registers
will be assigned their default values after H_RESET.
The content of the Address PROM locations (offsets
0h - Fh from the I/O or memory mapped I/O base ad-
dress) will be undefined.
EEPROM Auto-Detection
The Am79C972 controller uses the EESK/LED1/SFBD
pin to determine if an EEPROM is present in the sys-
tem. At the rising edge of CLK during the last clock dur-
Am79C972
ing which RST is asserted, the Am79C972 controller
will sample the value of the EESK/LED1/SFBD pin. If
the sampled value is a 1, then the Am79C972 controller
assumes that an EEPROM is present, and the EE-
PROM read operation begins shortly after the RST pin
is deasserted. If the sampled value of EESK/LED1/
SFBD is a 0, the Am79C972 controller assumes that an
external pulldown device is holding the EESK/LED1/
SFBD pin low, indicating that there is no EEPROM in
the system. Note that if the designer creates a system
that contains an LED circuit on the EESK/LED1/SFBD
pin, but has no EEPROM present, then the EEPROM
auto-detection function will incorrectly conclude that an
EEPROM is present in the system. However, this will
not pose a problem for the Am79C972 controller, since
the checksum verification will fail.
Direct Access to the Interface
The user may directly access the port through the
EEPROM register, BCR19. This register contains bits
that can be used to control the interface pins. By per-
forming an appropriate sequence of accesses to
BCR19, the user can effectively write to and read from
the EEPROM. This feature may be used by a system
configuration utility to program hardware configuration
information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
n I/O offsets 0h-Fh Address PROM locations
n BCR2
n BCR4
n BCR5
n BCR6
n BCR7
n BCR9
n BCR18
n BCR22
n BCR23
n BCR24
n BCR25
n BCR26
n BCR27
n BCR32
n BCR33
n BCR35
n BCR36
Miscellaneous Configuration
LED0 Status
LED1 Status
LED2 Status
LED3 Status
Full-Duplex Control
Burst and Bus Control
PCI Latency
PCI Subsystem Vendor ID
PCI Subsystem ID
SRAM Size
SRAM Boundary
SRAM Interface Control
MII Control and Status
MII Address
PCI Vendor ID
PCI
Capabilities (PMC) Alias Regis-
ter
Power
Management
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