am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 54

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

.
If RXON is cleared to 0, the Am79C972 controller will
never poll RDTE locations.
In order to avoid missing frames, the system should
have at least one RDTE available. To minimize poll ac-
tivity, two RDTEs should be available. In this case, the
poll operation will only consist of the check of the status
of the current TDTE.
A typical transmit poll is the product of the following
conditions:
1. Am79C972 controller does not own the current
2. Am79C972 controller does not own the current
3. Am79C972 controller does not own the current
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immedi-
ately perform a polling operation. If RDTE ownership
54
TDTE and TXDPOLL = 0 (CSR4, bit 12) and
TXON = 1 (CSR0, bit 4) and
the poll time has elapsed, or
TDTE and TXDPOLL = 0 and TXON = 1 and
a frame has just been received, or
TDTE and TXDPOLL = 0 and TXON = 1 and
a frame has just been transmitted.
TLE RES RLE RES
IADR[31:16]
CSR2
RES
Initialization
LADRF[63:32]
LADRF[31:0
RDRA[31:0]
TDRA[31:0]
PADR[31:0]
Block
PADR[47:32]
IADR[15:0]
CSR1
MODE
Figure 32. 32-Bit Software Model
Buffers
Am79C972
Buffers
Xmt
Rcv
1st
desc.
start
RMD
1st
desc.
start
TMD0
has not been previously established, then an RDTE
poll will be performed ahead of the TDTE poll. If the mi-
crocode is not executing the poll counting code when
the TDMD bit is set, then the demanded poll of the
TDTE will be delayed until the microcode returns to the
poll counting code.
The user may change the poll time value from the de-
fault of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47).
Transmit Descriptor Table Entry
If, after a Transmit Descriptor Table Entry (TDTE) ac-
cess, the Am79C972 controller finds that the OWN bit
of that TDTE is not set, the Am79C972 controller re-
sumes the poll time count and re-examines the same
TDTE at the next expiration of the poll time count.
If the OWN bit of the TDTE is set, but the Start of
Packet (STP) bit is not set, the Am79C972 controller
will immediately request the bus in order to clear the
OWN bit of this descriptor. (This condition would nor-
mally be found following a late collision (LCOL) or retry
(RTRY) error that occurred in the middle of a transmit
frame chain of buffers.) After resetting the OWN bit of
this descriptor, the Am79C972 controller will again im-
Buffer
Buffer
Data
Data
1
1
RMD
Rcv Descriptor
TMD1 TMD2 TMD3
N
Xmt Descriptor
M
Ring
RMD
Ring
Buffer
Buffer
N
Data
Data
2
M
2
RMD
N
M
2nd
desc.
start
2nd
desc.
start
RMD
N
TMD0
M
Buffer
Buffer
Data
Data
N
M
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