am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 102

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

PCI Expansion ROM Base Address Register
Offset 30h
The PCI Expansion ROM Base Address register is a
32-bit register that defines the base address, size and
address alignment of an Expansion ROM. It is located
at offset 30h in the PCI Configuration Space.
Bit
31-20
19-1
102
Name
ROMBASE Expansion ROM base address
ROMSIZE
Since the 12 most significant bits
of the base address are program-
mable, the host can map the Ex-
pansion
boundary.
When the Am79C972 controller
is enabled for Expansion ROM
access (ROMEN and MEMEN
are set to 1), it monitors the PCI
bus for a valid memory com-
mand. If the value on AD[31:2]
during the address phase of the
cycle falls between ROMBASE
and ROMBASE + 1M - 4, the
Am79C972 controller will drive
DEVSEL indicating it will respond
to the access.
ROMBASE is read and written by
the host. ROMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
Description
most significant 12 bits. These
bits are written by the host to
specify the location of the Expan-
sion ROM in all of memory space.
ROMBASE must be written with a
valid
Am79C972 Expansion ROM ac-
cess
ROMEN (PCI Expansion ROM
Base Address register, bit 0) and
MEMEN (PCI Command register,
bit 1).
ROM size. Read as zeros; write
operation have no effect. ROM-
SIZE indicates the maximum size
of the Expansion ROM the
Am79C972 controller can sup-
port. The host can determine the
Expansion ROM size by writing
FFFF FFFFh to the Expansion
ROM Base Address register. It
will read back a value of 0 in bit
is
address
ROM
enabled
on
before
by
any
setting
Am79C972
the
1M
0
PCI Capabilities Pointer Register
Offset 34h
Bit
7-0
PCI Interrupt Line Register
Offset 3Ch
The PCI Interrupt Line register is an 8-bit register that
is used to communicate the routing of the interrupt.
This register is written by the POST software as it ini-
tializes the Am79C972 controller in the system. The
register is read by the network driver to determine the
interrupt channel which the POST software has as-
signed to the Am79C972 controller. The PCI Interrupt
Line register is not modified by the Am79C972 control-
ler. It has no effect on the operation of the device.
The PCI Interrupt Line register is located at offset 3Ch
in the PCI Configuration Space. It is read and written by
ROMEN
Name
CAP_PTR
19-1, indicating an Expansion
ROM size of 1M.
Note that ROMSIZE only speci-
fies the maximum size of Expan-
sion
controller supports. A smaller
ROM can be used, too. The actu-
al size of the code in the Expan-
sion ROM is always determined
by reading the Expansion ROM
header.
by the host to enable access to
the
Am79C972 controller will only re-
spond to accesses to the Expan-
sion ROM when both ROMEN
and MEMEN (PCI Command reg-
ister, bit 1) are set to 1.
ROMEN is read and written by
the host. ROMEN is cleared by
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
Register is an 8-bit register that
points to a linked list of capabili-
ties implemented on this device.
This register has a default value
of 40h.
located at offset 34h in the PCI
Configuration Space. It is read
only.
Expansion ROM Enable. Written
Description
The PCI Capabilities pointer
The PCI Capabilities register is
Expansion
ROM
the
ROM.
Am79C972
The