am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 49

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

Burst FIFO DMA Transfers
Bursting is only performed by the Am79C972 controller
if the BREADE and/or BWRITE bits of BCR18 are set.
These bits individually enable/disable the ability of the
Am79C972 controller to perform burst accesses during
master read operations and master write operations,
respectively.
A burst transaction will start with an address phase, fol-
lowed by one or more data phases. AD[1:0] will always
be 0 during the address phase indicating a linear burst
order.
During FIFO DMA read operations, all byte lanes will
always be active. The Am79C972 controller will inter-
nally discard unused bytes. During the first and the last
data phases of a FIFO DMA burst write operation, one
or more of the byte enable signals may be inactive. All
other data phases will always write a complete DWord.
Figure 29 shows the beginning of a FIFO DMA write
with the beginning of the buffer not aligned to a DWord
boundary. The Am79C972 controller starts off by writ-
ing only three bytes during the first data phase. This op-
eration aligns the address for all other data transfers to
a 32-bit boundary so that the Am79C972 controller can
continue bursting full DWords.
If a receive buffer does not end on a DWord boundary,
the Am79C972 controller will perform a non-DWord
write on the last transfer to the buffer. Figure 30 shows
the final three FIFO DMA transfers to a receive buffer.
Since there were only nine bytes of space left in the re-
ceive buffer, the Am79C972 controller bursts three data
phases. The first two data phases write a full DWord,
the last one only writes a single byte.
Note that the Am79C972 controller will always perform
a DWord transfer as long as it owns the buffer space,
even when there are less than four bytes to write. For
example, if there is only one byte left for the current re-
ceive frame, the Am79C972 controller will write a full
DWord, containing the last byte of the receive frame in
the least significant byte position (BSWP is cleared to
0, CSR3, bit 2). The content of the other three bytes is
undefined. The message byte count in the receive de-
scriptor always reflects the exact length of the received
frame.
Am79C972
Figure 29. FIFO Burst Write At Start Of Unaligned
The Am79C972 controller will continue transferring
FIFO data until the transmit FIFO is filled to its high
threshold (read transfers) or the receive FIFO is emp-
tied to its low threshold (write transfers), or the
Am79C972 controller is preempted, and the PCI La-
tency Timer is expired. The host should use the values
in the PCI MIN_GNT and MAX_LAT registers to deter-
mine the value for the PCI Latency Timer.
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Buffer
0111
ADD
3
DATA
0001
PAR
4
DATA
PAR
5
0000
21485C-32
DATA
PAR
6
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