am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 53

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

Note that the value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus mas-
ter transfers.
Figure 32 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is set to 1.
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity
being performed by the Am79C972 controller, then the
Am79C972 controller will periodically poll the current
receive and transmit descriptor entries in order to as-
certain their ownership. If the TXDPOLL bit in CSR4 is
set, then the transmit polling function is disabled.
A typical polling operation consists of the following se-
quence. The Am79C972 controller will use the current
receive descriptor address stored internally to vector to
the appropriate Receive Descriptor Table Entry
TLE
RLE
IADR[31:16]
CSR2
Initialization
LADRF[47:32]
LADRF[63:48]
LADRF[31:16]
RES
RES
PADR[31:16]
PADR[47:32]
LADRF[15:0
PADR[15:0]
RDRA[15:0]
TDRA[15:0]
Block
MOD
TDRA[23:16]
RDRA[23:16]
IADR[15:0]
CSR1
Figure 31. 16-Bit Software Model
Buffers
Buffers
Xmt
Rcv
Am79C972
1st
desc.
1st
desc.
RMD
TMD
Buffer
(RDTE). It will then use the current transmit descriptor
address (stored internally) to vector to the appropriate
Transmit Descriptor Table Entry (TDTE). The accesses
will be made in the following order: RMD1, then RMD0
of the current RDTE during one bus arbitration, and
after that, TMD1, then TMD0 of the current TDTE dur-
ing a second bus arbitration. All information collected
during polling activity will be stored internally in the ap-
propriate CSRs, if the OWN bit is set (i.e., CSR18,
CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,
CSR52).
A typical receive poll is the product of the following con-
ditions:
1. Am79C972 controller does not own the current
2. Am79C972 controller does not own the next RDTE
Buffer
Data
Data
1
1
RMD
RDTE and the poll time has elapsed and
RXON = 1 (CSR0, bit 5), or
and there is more than one receive descriptor in the
ring and the poll time has elapsed and RXON = 1.
Rcv Descriptor
N
TMD
M
Xmt Descriptor
Ring
RMD
Buffer
Buffer
Data
N
TMD
Data
Ring
2
2
M
RMD
N
TMD
M
2nd
desc.
2nd
desc.
RMD0
N
TMD
M
Buffer
Buffer
Data
Data
M
N
21485C-34
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